This a IC2 design, which is simulated successfully in modelsim.

ic2\i2c_slave_model.v
...\i2c_slave_model.v.bak
...\ic2.cr.mti
...\ic2.mpf
...\spi_slave_model.v
...\spi_slave_model.v.bak
...\tst_bench_top.v
...\tst_bench_top.v.bak
...\wb_master_model.v
...\wb_master_model.v.bak
...\.ork\delay\verilog.asm
...\....\.....\verilog.rw
...\....\.....\_primary.dat
...\....\.....\_primary.dbs
...\....\.....\_primary.vhd
...\....\i2c_slave_model\verilog.asm
...\....\...............\verilog.rw
...\....\...............\_primary.dat
...\....\...............\_primary.dbs
...\....\...............\_primary.vhd
...\....\spi_slave_model\_primary.dat
...\....\...............\_primary.dbs
...\....\...............\_primary.vhd
...\....\tst_bench_top\verilog.asm
...\....\.............\verilog.rw
...\....\.............\_primary.dat
...\....\.............\_primary.dbs
...\....\.............\_primary.vhd
...\....\wb_master_model\verilog.asm
...\....\...............\verilog.rw
...\....\...............\_primary.dat
...\....\...............\_primary.dbs
...\....\...............\_primary.vhd
...\....\_info
...\....\.temp\vlogaa24gn
...\....\.....\vlogdmigi8
...\....\.....\vloge5gvq5
...\....\.....\vlogftsacv
...\....\.....\vlogjm6t0b
...\....\.....\vlogkra1jc
...\....\.....\vlogvq1rm4
...\....\.....\vlogxji2hj
...\....\.....\vlogzw7ivv
...\....\_vmake
...\....\delay
...\....\i2c_slave_model
...\....\spi_slave_model
...\....\tst_bench_top
...\....\wb_master_model
...\....\_temp
...\work
ic2

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