verilog HDL description uart program Received by the PC side and then+1 back。 SEU

formal01.fit.rpt
formal01.fit.smsg
formal01.fit.summary
formal01.flow.rpt
formal01.map.rpt
formal01.map.summary
formal01.pin
formal01.pof
formal01.qpf
formal01.qsf
formal01.qws
formal01.sof
formal01.tan.rpt
formal01.tan.summary
output_test.bsf
output_test.inc
system_ctrl.bsf
uart_receiver.bsf
uart_test.bsf
uart_transfer.bsf
db\formal01.asm.qmsg
..\formal01.asm.rdb
..\formal01.asm_labs.ddb
..\formal01.cbx.xml
..\formal01.cmp.bpm
..\formal01.cmp.cdb
..\formal01.cmp.ecobp
..\formal01.cmp.hdb
..\formal01.cmp.kpt
..\formal01.cmp.logdb
..\formal01.cmp.rdb
..\formal01.cmp.tdb
..\formal01.cmp0.ddb
..\formal01.cmp2.ddb
..\formal01.cmp_merge.kpt
..\formal01.db_info
..\formal01.eco.cdb
..\formal01.fit.qmsg
..\formal01.hier_info
..\formal01.hif
..\formal01.lpc.html
..\formal01.lpc.rdb
..\formal01.lpc.txt
..\formal01.map.bpm
..\formal01.map.cdb
..\formal01.map.ecobp
..\formal01.map.hdb
..\formal01.map.kpt
..\formal01.map.logdb
..\formal01.map.qmsg
..\formal01.map_bb.cdb
..\formal01.map_bb.hdb
..\formal01.map_bb.logdb
..\formal01.pre_map.cdb
..\formal01.pre_map.hdb
..\formal01.rtlv.hdb
..\formal01.rtlv_sg.cdb
..\formal01.rtlv_sg_swap.cdb
..\formal01.sgdiff.cdb
..\formal01.sgdiff.hdb
..\formal01.sld_design_entry.sci
..\formal01.sld_design_entry_dsc.sci
..\formal01.smart_action.txt
..\formal01.syn_hier_info
..\formal01.tan.qmsg
..\formal01.tis_db_list.ddb
..\logic_util_heursitic.dat
..\prev_cmp_formal01.asm.qmsg
..\prev_cmp_formal01.fit.qmsg
..\prev_cmp_formal01.map.qmsg
..\prev_cmp_formal01.qmsg
..\prev_cmp_formal01.tan.qmsg
incremental_db\compiled_partitions\formal01.root_partition.cmp.cdb
..............\...................\formal01.root_partition.cmp.dfp
..............\...................\formal01.root_partition.cmp.hdb
..............\...................\formal01.root_partition.cmp.kpt
..............\...................\formal01.root_partition.cmp.logdb
..............\...................\formal01.root_partition.cmp.rcfdb
..............\...................\formal01.root_partition.cmp.re.rcfdb
..............\...................\formal01.root_partition.map.cdb
..............\...................\formal01.root_partition.map.dpi
..............\...................\formal01.root_partition.map.hdb
..............\...................\formal01.root_partition.map.kpt
..............\README
src\clk_generator.v
...\output_test.v
...\system_ctrl.v
...\uart_receiver.v
...\uart_test.v
...\uart_transfer.v
clk_generator.bsf
formal01.asm.rpt
formal01.bdf
formal01.cdf
formal01.done
formal01.dpf
incremental_db\compiled_partitions
db
incremental_db
src

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