VHDL-FPGA-Verilog List Page 1006

VHDL-FPGA-Verilog list

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encoder104 Downloaded：0: One-hot code to binary code conversion, or 10 inputs 4 outputs the binary encoder verilog program.
Date : 2025-08-11 Size : 341kb User : li
enhanced_seven_seg Downloaded：0: Enable end with 7-segment decoder, active low, Enable is active high and achieve binary code to seven segment decoder encoding output enable is low as a whole.
Date : 2025-08-11 Size : 399kb User : li
mux4_with_en Downloaded：0: 4 with Enable input data selector, S0, S1, S2, C0, C1 as input, C1, C2 an enable input, P, Q, R, T as an output, c1c2 = 00 are all 0, the output, c1c2 = 01 are all the output 1, c1c2 = 10 time data selection, c1c2 = 11 c
Date : 2025-08-11 Size : 375kb User : li
src Downloaded：0: Xilinx FPGA-based digital frequency meter, including frequency measurement measuring duty cycle pulse testing, etc.
Date : 2025-08-11 Size : 13kb User : 黄伟
Cont_THS1207 Downloaded：0: FPGA control THS1207 multi-channel ADC' s verilog source code
Date : 2025-08-11 Size : 1.65mb User : 朱健
1bit-shumaguan-display Downloaded：0: EPM1270 VHDL 1-bit digital tube dynamic display. Complete document wallets
Date : 2025-08-11 Size : 276kb User : 丹丹
2channel-selector Downloaded：0: EPM1270 VHDL 2 way selector. Complete document wallets
Date : 2025-08-11 Size : 163kb User : 丹丹
D-trigger Downloaded：0: FPGA EPM1270 VHDL D flip-flop. Complete document wallets
Date : 2025-08-11 Size : 165kb User : 丹丹
3_8-decoder Downloaded：0: CPLD EPM1270 VHDL 3-8 decoder.
Date : 2025-08-11 Size : 184kb User : 丹丹
sw2reg Downloaded：0: Experimental use Nexys3 complete board Lab15: switch data is loaded into the register and display design and implementation. Suitable Nexys3 of the FPGA reference for beginners.
Date : 2025-08-11 Size : 166kb User : yf
lcd_control Downloaded：0: FPGA-based LCD display student number controls the veilog code
Date : 2025-08-11 Size : 353kb User : 朱健
VHDL Downloaded：0: Based on VHDL and CPLD development board, divider circuit circuit development.
Date : 2025-08-11 Size : 1kb User : 李伟

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