VHDL-FPGA-Verilog List Page 1008

VHDL-FPGA-Verilog list

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adc Downloaded：0: Based on the adc vhdl language debugger, program portability, right after the actual testing
Date : 2025-08-11 Size : 2kb User : 郭悦
saomiao Downloaded：0: Vhdl language-based digital control of dynamic scanning display program code, while adding a digital tube flashes, over and under range of led lights display alarm additional kinetic energy
Date : 2025-08-11 Size : 1kb User : 郭悦
lcd_at_nios_qii_part Downloaded：0: Implements a simple digital photo frame
Date : 2025-08-11 Size : 1.71mb User :
dds Downloaded：0: A dds signal generator, the original is the use of the 1/4 compression technology reduces the cost of rom thus leaving room to improve the precision
Date : 2025-08-11 Size : 124kb User : 千岛龙崎
Button_LED Downloaded：0: Verilog for MaxV
Date : 2025-08-11 Size : 270kb User : 阿源
Flicker_LED Downloaded：0: It s Flicker_LED code.Verilog for MaxV.
Date : 2025-08-11 Size : 170kb User : 阿源
OSC Downloaded：0: It s OSC code.Verilog for MaxV.
Date : 2025-08-11 Size : 131kb User : 阿源
HD_top_null Downloaded：0: It s HD quad code . VHDL for Altera s cyclone4
Date : 2025-08-11 Size : 4.41mb User : 阿源
divider Downloaded：0: its a very good divider based on Verilog HDL
Date : 2025-08-11 Size : 1kb User : 陈成
sgmii_latest[1].tar Downloaded：0: This core implements Physical Coding Sublayer of 1000BaseX transmission (IEEE 802.3 Clause36 and 37). This core can also be used for SGMII interface as this interface leverages 1000BaseX PCS. The differences between the
Date : 2025-08-11 Size : 15.8mb User : hejun
8b10_enc Downloaded：0: This program is used to do encoding according to 8B/10B protocol. The program has been written in VHDL
Date : 2025-08-11 Size : 3kb User : Deeptho
lvboqi_demo Downloaded：0: Fpga-based programmable filter design, verilog code written
Date : 2025-08-11 Size : 8.31mb User : 李康

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