Experimental use Nexys3 complete board Lab15: switch data is loaded into the register and display design and implementation. Suitable Nexys3 of the FPGA reference for beginners.

sw2reg\iseconfig\sw2reg.projectmgr
......\.........\sw2reg.xreport
......\par_usage_statistics.html
......\sw2reg.cmd_log
......\sw2reg.gise
......\sw2reg.lso
......\sw2reg.prj
......\sw2reg.syr
......\sw2reg.ucf
......\sw2reg.v
......\sw2reg.xise
......\sw2reg.xst
......\sw2regtop.bgn
......\sw2regtop.bit
......\sw2regtop.bld
......\sw2regtop.cmd_log
......\sw2regtop.drc
......\sw2regtop.lso
......\sw2regtop.ncd
......\sw2regtop.ngc
......\sw2regtop.ngd
......\sw2regtop.ngr
......\sw2regtop.pad
......\sw2regtop.par
......\sw2regtop.pcf
......\sw2regtop.prj
......\sw2regtop.ptwx
......\sw2regtop.stx
......\sw2regtop.syr
......\sw2regtop.twr
......\sw2regtop.twx
......\sw2regtop.unroutes
......\sw2regtop.ut
......\sw2regtop.xpi
......\sw2regtop.xst
......\sw2regtop_bitgen.xwbt
......\sw2regtop_envsettings.html
......\sw2regtop_guide.ncd
......\sw2regtop_map.map
......\sw2regtop_map.mrp
......\sw2regtop_map.ncd
......\sw2regtop_map.ngm
......\sw2regtop_map.xrpt
......\sw2regtop_ngdbuild.xrpt
......\sw2regtop_pad.csv
......\sw2regtop_pad.txt
......\sw2regtop_par.xrpt
......\sw2regtop_summary.html
......\sw2regtop_summary.xml
......\sw2regtop_usage.xml
......\sw2regtop_xst.xrpt
......\sw2reg_envsettings.html
......\sw2reg_summary.html
......\sw2reg_xst.xrpt
......\usage_statistics_webtalk.html
......\webtalk.log
......\webtalk_pn.xml
......\xlnx_auto_0_xdb\cst.xbcd
......\.st\work\work.sdbl
......\...\....\work.sdbx
......\_ngo\netlist.lst
......\.xmsgs\bitgen.xmsgs
......\......\map.xmsgs
......\......\ngdbuild.xmsgs
......\......\par.xmsgs
......\......\pn_parser.xmsgs
......\......\trce.xmsgs
......\......\xst.xmsgs
......\xst\dump.xst\sw2regtop.prj
......\...\dump.xst
......\...\projnav.tmp
......\...\work
......\ipcore_dir
......\iseconfig
......\xlnx_auto_0_xdb
......\xst
......\_ngo
......\_xmsgs
sw2reg

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