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Description: 基于fpga的正弦波发生器设计,有一定的参考价值,写的比较详细
Platform: | Size: 633427 | Author: qlg | Hits:

[SCMwave_generator

Description: 51单片机控制FPGA,通过DDS方式合成波形的发生器控制程序-51 MCU control FPGA, DDS waveform synthesis of the generator control procedures
Platform: | Size: 26624 | Author: shiyj | Hits:

[VHDL-FPGA-Verilogsin

Description: 基于fpga的正弦波发生器设计,有一定的参考价值,写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Platform: | Size: 632832 | Author: qlg | Hits:

[VHDL-FPGA-Verilogsin.tar

Description: 神奇的sin波生成verilog源码,非常简单的代码无需乘法即可生成sin,cos,值得搞算法的人借鉴-Magic sin wave generated Verilog source code, the code is very simple multiplication can be generated without sin, cos, worthy people from engaging in algorithm
Platform: | Size: 2048 | Author: yangyu | Hits:

[VHDL-FPGA-Verilogdds_using_FPGA

Description: 利用FPGA实现DDS经过编译没有错误。编译环境为QuartusII7.2,该环境集成了IP核,可以提高开发效率。-FPGA realization of the use of DDS compiled no errors. Compiler environment QuartusII7.2, the environment integrated IP core, can improve the development efficiency.
Platform: | Size: 100352 | Author: 白涛 | Hits:

[VHDL-FPGA-Verilogsin

Description: 用Verilog语言在FPGA内实现一256个采样点的正弦波,已尝试,挺好用的-Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
Platform: | Size: 104448 | Author: | Hits:

[VHDL-FPGA-Verilogsin

Description: 基于FPGA的正弦波发生器,可以产生不同频率的正弦波。-FPGA-based sine wave generator, can produce different frequency sine wave.
Platform: | Size: 609280 | Author: | Hits:

[Technology Managementfpga

Description: 采用正弦/ 余弦细分方案,通过嵌入cos/ sin 表格于FPGA 中,合理控制步进电机两相绕组的电流,实现斩波恒流均匀细分驱动,减小了步距角、提高了步进分辨率,最高细分达到256 。-Using sine/cosine segment program, by embedding cos/sin table in the FPGA, the reasonable control of two-phase stepper motor winding current to achieve constant current chopper driver uniform subdivision, reducing the step angle, increased step resolution, the highest segment to 256.
Platform: | Size: 233472 | Author: 邓志远 | Hits:

[assembly languagesin

Description: sin正弦波的产生 DDS FPGA VHDL语言-sin sine wave generation DDS FPGA VHDL language
Platform: | Size: 1731584 | Author: 王盛力 | Hits:

[VHDL-FPGA-VerilogFPGA

Description: sin函数 交通灯 加法器的vhdl代码 自写,参考-sin function
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilogsin-two-90

Description: 基于FPGA模拟DDS产生两路互为90度得正弦波,以此为依据,可做频率,相位可调的多路波形发生器-FPGA-based simulation DDS generates two sine wave was 90 degrees each other, as a basis to do the frequency, phase adjustable multi-channel waveform generator
Platform: | Size: 243712 | Author: huangshaobo | Hits:

[VHDL-FPGA-Verilogsin

Description: FPGA正弦波信号发生器,能产生完美的正弦波形-FPGA sine wave signal generator, can produce perfect sine wave
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilogsin

Description: 利用fpga实现低频率(100khz以下)的正弦信号发生,另外可以改频率。非常方便-The use of the fpga achieve low frequency (100khz below) sinusoidal signal, the other can change the frequency. Very convenient
Platform: | Size: 3587072 | Author: 阮志强 | Hits:

[ARM-PowerPC-ColdFire-MIPSsin

Description: 基于FPGA的正弦函数信号发生器的设计,及其模块的分析-Sine function signal generator in the FPGA design, module-based analysis
Platform: | Size: 2048 | Author: 李国林 | Hits:

[VHDL-FPGA-VerilogFPGA(QII)

Description: 数字信号发生器,FPGA做的仿真程序,包含三角波、锯齿波、正弦波、方波等共六种波形。-FPGA AND alter SIN SAN JIAO BO JUCHIBO FANG BO
Platform: | Size: 4196352 | Author: 小华 | Hits:

[VHDL-FPGA-VerilogSIN-MODULATE-BASED-FPGA

Description: 对正弦波进行调制,下载到FPGA的硬件环境中,运行后用示波器检测,结果可行-On the sine wave modulation, downloaded to the FPGA hardware environment, running with an oscilloscope, and the results feasible
Platform: | Size: 1015808 | Author: 刘毓博 | Hits:

[ELanguagesin-sanj

Description: 基于FPGA的可调幅度频率的正弦波、三角波、锯齿波、矩形波发生器-FPGA-based adjustable amplitude sine wave frequency, triangle wave, sawtooth, square wave generator
Platform: | Size: 710656 | Author: may | Hits:

[VHDL-FPGA-Verilogverilog-sin

Description: FPGA开发sin波形,用verilog写的正弦波发生器。-FPGA development sin wave with verilog write sine wave generator
Platform: | Size: 7168 | Author: 蒋壮 | Hits:

[Documentscordic_ds249

Description: FPGA开发过程中的IP核,用于计算正弦,余弦和正切等。(IP core used in FPGA design to calculate cos and sin.)
Platform: | Size: 333824 | Author: 张扬1 | Hits:

[Embeded-SCM DevelopSIN

Description: 基于fpga实现信号发生器,本设计采用方法为基于dds原理产生正线波信号输出。(DDS wave signal output line.)
Platform: | Size: 2661376 | Author: 落地浮尘 | Hits:
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