sin Verilog language used in the FPGA to achieve o

Title: sin

Category:
VHDL-FPGA-Verilog
Tags:
[C/C++] [源码]
File Size:
102kb
Update:
2012-11-26
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Description: Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~

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File list (Check if you may need any files):

sine
....\default.cfg
....\default.cfg.bck
....\ROM.DAT
....\rom16x7.v
....\sgen.c
....\sim.vc
....\simv.daidir
....\...........\01j9_1.daidb
....\...........\3e3i_1.daidb
....\...........\vcs.dailu
....\...........\vcs_mstr.daidb
....\simv.exe
....\simv.exp
....\simv.lib
....\sine.v
....\sinetest.v
....\vcdplus.vpd
....\wave.bat

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