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[Program doc] dkljfkjls

Description: RISC处理器设计.ppt RISC处理器设计.ppt RISC处理器设计.ppt-RISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. PptRISC processor design. Ppt
Platform: | Size: 292864 | Author: appolo | Hits:

[VHDL-FPGA-Verilog] OR1200_verilog

Description: or1200开源risc cpu的verilog描述实现，cpu源代码分析与芯片设计一书的源码-or1200 open source Verilog description of the risc cpu realize, cpu source code analysis and chip design source book
Platform: | Size: 204800 | Author: yu | Hits:

[Windows Develop] RISC_8

Description: 经过验证的8位RISC-CPU源代码，verilog代码，附：汇编测试源代码，而且测试通过。-Verified 8 RISC-CPU source code, verilog code, attached: the compilation of the test source code, and test.
Platform: | Size: 173056 | Author: WangYong | Hits:

[Other] embedded_risc.tar

Description: 是一个用于soc的32bit risc核，文件包括了核的rtl代码，文档、testbench码。-it is about the 32bit risc core for soc design.
Platform: | Size: 102400 | Author: 杨力 | Hits:

[Editor] processor.tar

Description: i need of vhdl code for 32-bit risc processor
Platform: | Size: 48128 | Author: ganesh | Hits:

[Other] risc

Description: 基于quartus II软件 用verilog 语言描述的精简指令CPU-quartus II verilog
Platform: | Size: 1259520 | Author: xu | Hits:

[Other] cputest

Description: 自己刚写的一个RISC的cpu，位宽16，主要是测试其中的逻辑，数据宽度是一位，可以很容易扩展-Writing just one of their own RISC the cpu, bit 16, are testing one of the main logic, data width, a, can be easily extended
Platform: | Size: 21504 | Author: myliu | Hits:

[VHDL-FPGA-Verilog] alu

Description: verilog code for alu in RISC processor
Platform: | Size: 1024 | Author: John jose | Hits:

[Other] Jh_cpu

Description: Jh_cpu is a cpu with 12 address,8 data bus, adn give direct address ,indirect address two addressin way.-This VHDl code can provide a total clear and detail process to create a basic function risc cpu.
Platform: | Size: 52224 | Author: ananliu1 | Hits:

[Other] computer2

Description: 一款8位RISC MCU的设计-An 8-bit RISC MCU Design .........
Platform: | Size: 794624 | Author: steven | Hits:

[VHDL-FPGA-Verilog] computer12

Description: 基于FPGA的八位RISC CPU的设计-FPGA-based RISC CPU design eight ....
Platform: | Size: 64512 | Author: steven | Hits:

[DVD] MTK_DVD_MT1389_RISC_command_mode

Description: MTK DVD MT1389 RISC命令方式-MTK DVD MT1389 RISC command mode
Platform: | Size: 381952 | Author: shur | Hits:

[DVD] MTK_DVD_1389H_CHIP_8032andRISC

Description: MTK_DVD_1389H_CHIP_8032 and RISC CODE
Platform: | Size: 27755520 | Author: shur | Hits:

[VHDL-FPGA-Verilog] 8risc

Description: 8位RISC CPU,包括alu,count,machine-8 bit risc cpu
Platform: | Size: 3072 | Author: 刘成诚 | Hits:

[Software Engineering] risc32

Description: VHDL设计实例与仿真中的32位risc代码，经仿真确定可以通过-VHDL design and simulation of the 32-bit risc code, as determined by simulation
Platform: | Size: 712704 | Author: Jack | Hits:

[Software Engineering] 32RISC

Description: 32位risc设计过程步骤讲解，非常专业，希望对大家有帮助！-32 steps to explain the design process risc, very professional, we want to help!
Platform: | Size: 2991104 | Author: 田雨 | Hits:

[DSP program] risc_cpu

Description: This an example of simple RISC CPU implemented in SystemC.-This is an example of simple RISC CPU implemented in SystemC.
Platform: | Size: 41984 | Author: R Zhang | Hits:

[Software Engineering] CPU_Architecture

Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism. -Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
Platform: | Size: 2506752 | Author: Amit Adoni | Hits:

[VHDL-FPGA-Verilog] CPU_Architecture

Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism. -Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
Platform: | Size: 2388992 | Author: Amit Adoni | Hits:

[Windows Develop] 8BitRISC_CPU(VERILOG)

Description: 8位risc内核源代码，内有体统框图，较其他详细。适合初学者学习-8-bit risc kernel source code, there are decency diagram, compared with other details. Suitable for beginners to learn
Platform: | Size: 77824 | Author: lsj | Hits:
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