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[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

Description: 使用Verilog语言实现的RISC精简指令集CPU IP核，该CPU具有32位数据宽度，5级流水线结构和指令预判和中断处理功能，适合Verilog语言深入学习者参考。-Using the Verilog language implementation of RISC Reduced Instruction Set CPU IP cores, the CPU has a 32-bit data width, 5-stage pipeline structure and instruction pre-judgment and interrupt handling functions for Verilog language learners in depth reference.
Platform: | Size: 33792 | Author: 张秋光 | Hits:

[ARM-PowerPC-ColdFire-MIPS] RISC-CPU-ARM

Description: 32位RISC CPU ARM芯片的应用和选型-32-bit RISC CPU ARM chip application and selection
Platform: | Size: 16384 | Author: guoqian | Hits:

[VHDL-FPGA-Verilog] 8-bit-risc-in-vhdl.vhd

Description: risc processor in vhdl
Platform: | Size: 4096 | Author: pradeep | Hits:

[Software Engineering] RISC-ARM

Description: RISC 架构下的ARM 微处理器应用研究,：该文主要介绍了当下流行的嵌入式系统的RISC 架构下微处理器ARM，分析ARM 微处理器适应嵌入式系统的特点和它的相关产品适用的领域及其广阔的发展前景-Under the frame of RISC ARM microprocessor application research, : it introduces the current popular embedded system under the RISC ARCHITECTURE MICROPROCESSOR ARM, analysis of ARM microprocessor adapted to the characteristics of embedded system and its related products applicable fields and broad development prospect
Platform: | Size: 104448 | Author: 曹瑞翠 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU-design

Description: 16位RISC-CPU设计，高四位为操作码，低12位为地址，寻址空间位4KB。包含12条指令（预设16条指令），3个基本测试文件及其Modelsim仿真结果。-16-bit RISC-CPU design, the high four bits for the opcode, the lower 12 address, the address space of 4KB. Consists of 12 instructions (default 16 instructions), the three basic test file and Modelsim simulation results.
Platform: | Size: 413696 | Author: yu | Hits:

[Other] risc

Description: RISC是一种执行较少类型计算机指令的微处理器，起源于80 年代的MIPS主机（即RISC 机），RISC机中采用的微处理器统称RISC处理器。这样一来，它能够以更快的速度执行操作（每秒执行更多百万条指令，即MIPS）。因为计算机执行每个指令类型都需要额外的晶体管和电路元件，计算机指令集越大就会使微处理器更复杂，执行操作也会更慢。 -RISC is a microprocessor performs fewer types of computer instructions, originated in the 1980s MIPS host (RISC machine), collectively, the RISC processor RISC machine microprocessor. As a result, it is able to perform operations at a faster rate (perform more millions of instructions per second, or MIPS). Because the computer to execute each instruction type requires the additional transistor and the circuit element, the larger set of computer instructions would make more complex microprocessor, perform an action will be slower.
Platform: | Size: 608256 | Author: 郭加园 | Hits:

[VHDL-FPGA-Verilog] RISC---8

Description: 集成RISC-CPU芯片设计，很实用的程序，对初学FPGA的同学有很大的帮助奥-Integrated RISC-CPU chip design, very practical program, beginner FPGA classmates help Austrian
Platform: | Size: 195584 | Author: 天空 | Hits:

[VHDL-FPGA-Verilog] Simply-RISC-M1-Core.tar

Description: Simply RISC M1 Core.tar
Platform: | Size: 281600 | Author: Archie | Hits:

[Software Engineering] 1632-bit-RISC-processor-S3C2410A

Description: 16/32位RISC处理器S3C2410A-16/32-bit RISC processor S3C2410A
Platform: | Size: 1355776 | Author: 于金水 | Hits:

[Other] Guide-To-RISC-Processors---For-Programmers-And-En

Description: RISC assembly language in MIPS processor
Platform: | Size: 1092608 | Author: Dreamer | Hits:

[Linux-Unix] btcx-risc

Description: bt848/bt878/cx2388x risc code generator.
Platform: | Size: 3072 | Author: gfthnr | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 精简指令集RISC-CPU 可以实现阶乘运算 verilog代码编写含有测试平台-Reduced instruction set RISC-CPU test platform can implement written in the factorial operator verilog code contains
Platform: | Size: 3288064 | Author: | Hits:

[VHDL-FPGA-Verilog] cpu-risc

Description: wb_switch，cpu设计，精简指令cup设计-wb_switch，opencore，risc cpu design。
Platform: | Size: 36864 | Author: 浮萍 | Hits:

[VHDL-FPGA-Verilog] RISC-CPU

Description: 精简指令集 CPU 通过仿真验证正确 (使用之前务必看readme文件，和结构图!) 1. 此cpu是夏宇闻 verilog数字系统设计教程中最后一章的例程。 2. 学习时务必先搞明白框图原理，和数据流动！！！ 3. 牢记主状态机中一条指令周期中传输的16bit=3bit指令+13bit地址。 4. 理解数据总线，和地址总线。区分数据和地址。 5. 仔细调试，因为书中有很多小错误。程序经过quartusii编译通过，另外经过modelsim仿真正确。-RISC CPU properly verified by simulation (using the previously sure to see the readme file and structure chart!) This CPU is the last chapter Xia Wen verilog Digital System Design Guide routine. 2 study sure to thoroughly understand block diagram of the principle, and the flow of data! ! ! Keep in mind one instruction cycle in the transmission of the main state machine the 16bit = 3bit instruction+13bit address. 4 understand the data bus and address bus. Between data and addresses. Carefully debugging, because there are many small errors in the book. The program compiled through quartusii by the addition after modelsim simulation.
Platform: | Size: 4337664 | Author: 刘栋 | Hits:

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[VHDL-FPGA-Verilog] 32bit-RISC-CPU-IP

[ARM-PowerPC-ColdFire-MIPS] RISC-CPU-ARM

[VHDL-FPGA-Verilog] 8-bit-risc-in-vhdl.vhd

[Software Engineering] RISC-ARM

[VHDL-FPGA-Verilog] RISC-CPU-design

[Other] risc

[VHDL-FPGA-Verilog] RISC---8

[VHDL-FPGA-Verilog] Simply-RISC-M1-Core.tar

[Software Engineering] 1632-bit-RISC-processor-S3C2410A

[Other] Guide-To-RISC-Processors---For-Programmers-And-En

[Linux-Unix] btcx-risc

[VHDL-FPGA-Verilog] RISC-CPU

[VHDL-FPGA-Verilog] cpu-risc

[VHDL-FPGA-Verilog] RISC-CPU

[VHDL-FPGA-Verilog] PIC16F5X-RISC

[Other] risc-4-way-lru-processor-verilog

[VHDL-FPGA-Verilog] pipeline-RiSC

[VHDL-FPGA-Verilog] Mini-Risc-core

[VHDL-FPGA-Verilog] RISC-CODE

[VHDL-FPGA-Verilog] RISC-CPU

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