Description: In this thesis, after in-depth understanding of Wishbone bus protocol and DMA technology, present a design concept of a DMAC integrated into a Wishbone bus based SOC. The DMAC designed in this thesis contains thirty-one programmable DMA channels, which can handle multiple DMA transfer request. As the data is transmitted over the Wishbone bus, the DMAC provides two Wishbone interfaces that can act as a host interface or as a slave interface. When several peripherals issue DMA transfer request at the same time, the DMAC adopts the combination of cyclic priority and dynamic priority to realize the secondary arbitration function of channel arbiter. In order to improve the transmission efficiency, the DMAC not only supports the transmission of data blocks, but also supports efficient scatter/gather DMA transfer mode.
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File list (Check if you may need any files):
| Filename | Size | Date |
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| dma_rtl\tcl_stacktrace.txt | 626 | 2017-04-07
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| dma_rtl\tests.v | 59782 | 2001-09-07
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| dma_rtl\test_bench_top.v | 70396 | 2018-01-18
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| dma_rtl\test_bench_top.v.bak | 70402 | 2018-01-18
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| dma_rtl\transcript | 666 | 2017-04-23
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| dma_rtl\wb_dma_ch_arb.v | 50454 | 2002-02-01
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| dma_rtl\wb_dma_ch_pri_enc.v | 11678 | 2002-02-01
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| dma_rtl\wb_dma_ch_rf.v | 16347 | 2002-02-01
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| dma_rtl\wb_dma_ch_sel.v | 54344 | 2002-02-01
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| dma_rtl\wb_dma_de.v | 19490 | 2002-02-01
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| dma_rtl\wb_dma_defines.v | 4909 | 2002-02-01
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| dma_rtl\wb_dma_inc30r.v | 3939 | 2002-02-01
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| dma_rtl\wb_dma_pri_enc_sub.v | 5042 | 2002-02-01
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| dma_rtl\wb_dma_rf.v | 63233 | 2002-02-01
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| dma_rtl\wb_dma_top.v | 32385 | 2002-02-01
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| dma_rtl\wb_dma_wb_if.v | 7147 | 2002-02-01
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| dma_rtl\wb_dma_wb_mast.v | 5776 | 2002-02-01
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| dma_rtl\wb_dma_wb_slv.v | 5975 | 2018-01-18
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| dma_rtl\wb_dma_wb_slv.v.bak | 5975 | 2002-02-01
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| dma_rtl\wb_mast_model.v | 10981 | 2002-02-01
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| dma_rtl\wb_model_defines.v | 3142 | 2002-02-01
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| dma_rtl\wb_slv_model.v | 5018 | 2002-02-01
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| dma_rtl | 0 | 2018-03-21 |
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