Description: Achieve dsp and fpga verilog asynchronous implementation of the emif, enabling asynchronous reading and writing as well as the corresponding function module control, the document contains graphics, and after the simulation waveform simulation testing procedures, operating environment quartus ii11.0, simulation environment mmodelsim se 6.5d
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emif_tt
.......\Thumbs.db
.......\sim
.......\...\dec_data.txt
.......\...\emif_tt.cr.mti
.......\...\emif_tt.mpf
.......\...\rom_data_fft.mif
.......\...\rom_data_fft_ini.mif
.......\...\rom_data_fft_ini.ver
.......\...\rom_data_ini.mif
.......\...\vsim.wlf
.......\...\work
.......\...\....\_info
.......\...\....\_temp
.......\...\....\_vmake
.......\...\....\butterfly
.......\...\....\.........\_primary.dat
.......\...\....\.........\_primary.dbs
.......\...\....\.........\_primary.vhd
.......\...\....\.........\verilog.asm
.......\...\....\.........\verilog.rw
.......\...\....\control
.......\...\....\.......\_primary.dat
.......\...\....\.......\_primary.dbs
.......\...\....\.......\_primary.vhd
.......\...\....\.......\verilog.asm
.......\...\....\.......\verilog.rw
.......\...\....\data_input
.......\...\....\..........\_primary.dat
.......\...\....\..........\_primary.dbs
.......\...\....\..........\_primary.vhd
.......\...\....\..........\verilog.asm
.......\...\....\..........\verilog.rw
.......\...\....\data_output
.......\...\....\...........\_primary.dat
.......\...\....\...........\_primary.dbs
.......\...\....\...........\_primary.vhd
.......\...\....\...........\verilog.asm
.......\...\....\...........\verilog.rw
.......\...\....\emif_brg
.......\...\....\........\_primary.dat
.......\...\....\........\_primary.dbs
.......\...\....\........\_primary.vhd
.......\...\....\........\verilog.asm
.......\...\....\........\verilog.rw
.......\...\....\fft
.......\...\....\...\_primary.dat
.......\...\....\...\_primary.dbs
.......\...\....\...\_primary.vhd
.......\...\....\...\verilog.asm
.......\...\....\...\verilog.rw
.......\...\....\fifo_out
.......\...\....\........\_primary.dat
.......\...\....\........\_primary.dbs
.......\...\....\........\_primary.vhd
.......\...\....\........\verilog.asm
.......\...\....\........\verilog.rw
.......\...\....\mult16x16
.......\...\....\.........\_primary.dat
.......\...\....\.........\_primary.dbs
.......\...\....\.........\_primary.vhd
.......\...\....\.........\verilog.asm
.......\...\....\.........\verilog.rw
.......\...\....\overflow_detect
.......\...\....\...............\_primary.dat
.......\...\....\...............\_primary.dbs
.......\...\....\...............\_primary.vhd
.......\...\....\...............\verilog.asm
.......\...\....\...............\verilog.rw
.......\...\....\ram64x36_dp
.......\...\....\...........\_primary.dat
.......\...\....\...........\_primary.dbs
.......\...\....\...........\_primary.vhd
.......\...\....\...........\verilog.asm
.......\...\....\...........\verilog.rw
.......\...\....\reg_ctrl_fft
.......\...\....\............\_primary.dat
.......\...\....\............\_primary.dbs
.......\...\....\............\_primary.vhd
.......\...\....\............\verilog.asm
.......\...\....\............\verilog.rw
.......\...\....\rom64@x32
.......\...\....\.........\_primary.dat
.......\...\....\.........\_primary.dbs
.......\...\....\.........\_primary.vhd
.......\...\....\.........\verilog.asm
.......\...\....\.........\verilog.rw
.......\...\....\rom_data_fft
.......\...\....\............\_primary.dat
.......\...\....\............\_primary.dbs
.......\...\....\............\_primary.vhd
.......\...\....\............\verilog.asm
.......\...\....\............\verilog.rw
.......\...\....\shift
.......\...\....\.....\_primary.dat
.......\...\....\.....\_primary.dbs
.......\...\....\.....\_primary.vhd
.......\...\....\.....\verilog.asm
.......\...\....\.....\verilog.rw
.......\...\....\tb_fft
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