Title:
grlib-gpl-1.0.21-b3848.tar
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Description: GRLIP IP blocks mapped on Virtex2,
Actel-AX and typical ASIC technologies. The area depends strongly on configuration options (generics),
optimization constraints and used synthesis tools. The data in the table should therefore be seen
as an indication only. The tools used to obtain the area was Synplify-8.1 for FPGA and Synopsys DC
for ASIC. The LUT area for Altera Stratix devices is roughly the same as for Virtex2. Using XST
instead of Synplify for Xilinx FPGAs gives typically 15 larger area.
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