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Title: zuizhongdianti Download
 Description: it is a elevator controller.
 Downloaders recently: [More information of uploader estella126]
 To Search:
  • [dianti] - using VHDL description was complicated l
  • [count] - Using VHDL written 4,7,40,64,84 counter,
File list (Check if you may need any files):
zuizhongdianti\.lso
..............\deal.v
..............\device_usage_statistics.html
..............\dfd.cel
..............\dfd.ucf
..............\ecd.v
..............\ecd_v.udo
..............\eee.v
..............\eee_v.udo
..............\Find_Best_Lift.prj
..............\Find_Best_Lift.stx
..............\Find_Best_Lift.v
..............\Find_Best_Lift.xst
..............\inp.v
..............\Input_module.v
..............\input_top.v
..............\lift_ucf.ucf
..............\liu.v
..............\liu_v.fdo
..............\liu_v.udo
..............\netgen\par\top_timesim.nlf
..............\......\...\top_timesim.sdf
..............\......\...\top_timesim.v
..............\......\synthesis\top_synthesis.nlf
..............\......\.........\top_synthesis.v
..............\Show_info.prj
..............\Show_info.stx
..............\Show_info.v
..............\Show_info.xst
..............\single_CU.prj
..............\single_CU.stx
..............\single_CU.v
..............\single_CU.xst
..............\test.v
..............\test_Find.v
..............\test_Find_v.udo
..............\test_lift.v
..............\test_lift_v.tdo
..............\test_lift_v.udo
..............\te_in2.v
..............\te_in2_v.udo
..............\timing.twr
..............\top.bgn
..............\top.bit
..............\top.bld
..............\top.cmd_log
..............\top.drc
..............\top.lso
..............\top.ncd
..............\top.ngc
..............\top.ngd
..............\top.ngr
..............\top.pad
..............\top.par
..............\top.pcf
..............\top.prj
..............\top.stx
..............\top.syr
..............\top.twr
..............\top.twx
..............\top.unroutes
..............\top.ut
..............\top.v
..............\top.xpi
..............\top.xst
..............\top_guide.ncd
..............\top_map.map
..............\top_map.mrp
..............\top_map.ncd
..............\top_map.ngm
..............\top_pad.csv
..............\top_pad.txt
..............\top_prev_built.ngd
..............\top_summary.html
..............\top_summary.xml
..............\top_usage.xml
..............\transcript
..............\vsim.wlf
..............\work\@find_@best_@lift\verilog.asm
..............\....\.................\_primary.dat
..............\....\.................\_primary.vhd
..............\....\.input_module\verilog.asm
..............\....\.............\_primary.dat
..............\....\.............\_primary.vhd
..............\....\.show_info\verilog.asm
..............\....\..........\_primary.dat
..............\....\..........\_primary.vhd
..............\....\deal\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\ecd_v\verilog.asm
..............\....\.....\_primary.dat
..............\....\.....\_primary.vhd
..............\....\.ee_v\verilog.asm
..............\....\.....\_primary.dat
..............\....\.....\_primary.vhd
..............\....\glbl\verilog.asm
..............\....\....\_primary.dat
..............\....\....\_primary.vhd
..............\....\inp\verilog.asm
    

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