Description: EDA experiment: to master the combination of the circuit VHDL description of the basic methods, learn to use QuatusII of the VHDL code synthesis and simulation, timing simulation function can be used by the design module of the simulation test. (4 binary sequence generator comparator design of intersection traffic lights)
To Search:
- [comparison] - 4-bit binary comparator, compare two bin
- [VHDLtest] - Sequence Detector Design 1. Purpose of t
- [qiangda] - EDA curriculum design intelligence Respo
File list (Check if you may need any files):
李源02065029\A3\A3.asm.rpt
............\..\A3.done
............\..\A3.fit.rpt
............\..\A3.fit.smsg
............\..\A3.fit.summary
............\..\A3.flow.rpt
............\..\A3.map.rpt
............\..\A3.map.summary
............\..\A3.pin
............\..\A3.qpf
............\..\A3.qsf
............\..\A3.qws
............\..\A3.sim.rpt
............\..\A3.tan.rpt
............\..\A3.vhd
............\..\A3.vwf
............\..\A3_assignment_defaults.qdf
............\..\db\A3.cbx.xml
............\..\..\A3.cmp.logdb
............\..\..\A3.cmp.rdb
............\..\..\A3.db_info
............\..\..\A3.eco.cdb
............\..\..\A3.eds_overflow
............\..\..\A3.fit.qmsg
............\..\..\A3.fit.rpt.tmp
............\..\..\A3.flow.rpt.tmp
............\..\..\A3.fnsim.cdb
............\..\..\A3.fnsim.hdb
............\..\..\A3.fnsim.qmsg
............\..\..\A3.hier_info
............\..\..\A3.hif
............\..\..\A3.map.bpm
............\..\..\A3.map.cdb
............\..\..\A3.map.ecobp
............\..\..\A3.map.hdb
............\..\..\A3.map.logdb
............\..\..\A3.map.qmsg
............\..\..\A3.map_bb.cdb
............\..\..\A3.map_bb.hdb
............\..\..\A3.map_bb.hdbx
............\..\..\A3.map_bb.logdb
............\..\..\A3.pre_map.cdb
............\..\..\A3.pre_map.hdb
............\..\..\A3.psp
............\..\..\A3.root_partition.map.atm
............\..\..\A3.root_partition.map.hdbx
............\..\..\A3.root_partition.map.info
............\..\..\A3.rtlv.hdb
............\..\..\A3.rtlv_sg.cdb
............\..\..\A3.rtlv_sg_swap.cdb
............\..\..\A3.sgdiff.cdb
............\..\..\A3.sgdiff.hdb
............\..\..\A3.sim.cvwf
............\..\..\A3.sim.hdb
............\..\..\A3.sim.qmsg
............\..\..\A3.simfam
............\..\..\A3.sld_design_entry.sci
............\..\..\A3.sld_design_entry_dsc.sci
............\..\..\A3.syn_hier_info
............\..\..\A3.tis_db_list.ddb
............\..\..\A3.tmw_info
............\..\..\prev_cmp_A3.fit.qmsg
............\..\..\prev_cmp_A3.map.qmsg
............\..\..\prev_cmp_A3.qmsg
............\..\..\prev_cmp_A3.sim.qmsg
............\..\..\wed.wsf
............\..\prev_cmp_A3.qmsg
............\..\图形.doc
............\B3\B3.asm.rpt
............\..\B3.done
............\..\B3.fit.rpt
............\..\B3.fit.smsg
............\..\B3.fit.summary
............\..\B3.flow.rpt
............\..\B3.map.rpt
............\..\B3.map.summary
............\..\B3.pin
............\..\B3.qpf
............\..\B3.qsf
............\..\B3.qws
............\..\B3.sim.rpt
............\..\B3.tan.rpt
............\..\B3.tan.summary
............\..\B3.vhd
............\..\B3.vwf
............\..\db\B3.asm.qmsg
............\..\..\B3.cbx.xml
............\..\..\B3.cmp.bpm
............\..\..\B3.cmp.cdb
............\..\..\B3.cmp.ecobp
............\..\..\B3.cmp.hdb
............\..\..\B3.cmp.logdb
............\..\..\B3.cmp.rdb
............\..\..\B3.cmp.tdb
............\..\..\B3.cmp0.ddb
............\..\..\B3.cmp_bb.cdb
............\..\..\B3.cmp_bb.hdb
............\..\..\B3.cmp_bb.logdb
............\..\..\B3.cmp_bb.rcf
............\..\..\B3.dbp
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