- Category:
- Other systems
- Tags:
-
- File Size:
- 20kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- nmh_cd
Description: pipe alu, successfully implement add, minus, multiplication,and logic operation
- [ALU] - Realize using Verilog ALU, realize a var
- [ALU-FP] - ALU floating point 8 bit
- [32Bitaludesign] - Design of simple 32 bit alu for SPARTAN
File list (Check if you may need any files):
pipe ALU
........\ALU_top.vhd
........\bit_adder.vhd
........\Fu_adder.vhd
........\logic_operation_module.vhd
........\mutilp.vhd
........\Pipe_adder.vhd
........\SHIFTER_MODULE.VHD
........\substractor.vhd
........\subs_pipe.vhd
........\test_adder.vhd
........\test_alu.vhd
........\test_bit_adder.vhd
........\test_controller.vhd
........\test_ctrl.vhd
........\test_mul.vhd
........\test_multi.vhd
........\test_pipe_adder.vhd
........\test_pipe_mul.vhd
........\test_sub.vhd
........\tst_sub.vhd
........\Unit_controller.vhd
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