ChipScopeTutorial\2005152257773813.bmp
.................\bmps\analyzer_1.bmp
.................\....\analyzer_2.bmp
.................\....\analyzer_3.bmp
.................\....\analyzer_4.bmp
.................\....\analyzer_5.bmp
.................\....\analyzer_6.bmp
.................\....\analyzer_7.bmp
.................\....\analyzer_8.bmp
.................\....\chipscope_1.bmp
.................\....\chipscope_2.bmp
.................\....\chipscope_3.bmp
.................\....\chipscope_4.bmp
.................\....\chipscope_5.bmp
.................\....\chipscope_6.bmp
.................\....\chipscope_7.bmp
.................\....\chipscope_8.bmp
.................\....\chipscope_9.bmp
.................\....\chipscope_a.bmp
.................\....\chipscope_b.bmp
.................\....\ise_1.bmp
.................\....\ise_2.bmp
.................\....\modelsim_1.bmp
.................\....\modelsim_2.bmp
.................\....\synplify_1.bmp
.................\....\synplify_2.bmp
.................\....\Thumbs.db
.................\bmps
.................\chipscope\icon.arg
.................\.........\icon.edn
.................\.........\icon.ncf
.................\.........\icon_synplicity_example.v
.................\.........\icon_synplicity_verilog_example.arg
.................\.........\ila.arg
.................\.........\ila.cdc
.................\.........\ila.edn
.................\.........\ila.ncf
.................\.........\ila_synplicity_example.v
.................\.........\ila_synplicity_verilog_example.arg
.................\chipscope
.................\Chipscope 简明教程.pdf
.................\rtl\lfsr.v
.................\...\lfsr_tb.v
.................\...\testbench\lfsr_tb.cr.mti
.................\...\.........\lfsr_tb.mpf
.................\...\.........\transcript
.................\...\.........\vsim.wlf
.................\...\.........\wave.do
.................\...\.........\.ork\lfsr\verilog.asm
.................\...\.........\....\....\_primary.dat
.................\...\.........\....\....\_primary.vhd
.................\...\.........\....\lfsr
.................\...\.........\....\...._tb\verilog.asm
.................\...\.........\....\.......\_primary.dat
.................\...\.........\....\.......\_primary.vhd
.................\...\.........\....\lfsr_tb
.................\...\.........\....\_info
.................\...\.........\work
.................\...\testbench
.................\rtl
.................\sp&r\place&route\lfsr\.untf
.................\....\...........\....\automake.log
.................\....\...........\....\bitgen.ut
.................\....\...........\....\lfsr.bgn
.................\....\...........\....\lfsr.bit
.................\....\...........\....\lfsr.bld
.................\....\...........\....\lfsr.cmd_log
.................\....\...........\....\lfsr.dhp
.................\....\...........\....\lfsr.drc
.................\....\...........\....\lfsr.mrp
.................\....\...........\....\lfsr.nc1
.................\....\...........\....\lfsr.ncd
.................\....\...........\....\lfsr.ngd
.................\....\...........\....\lfsr.ngm
.................\....\...........\....\lfsr.npl
.................\....\...........\....\lfsr.pad
.................\....\...........\....\lfsr.pad_txt
.................\....\...........\....\lfsr.par
.................\....\...........\....\lfsr.pcf
.................\....\...........\....\lfsr.placed_ncd_tracker
.................\....\...........\....\lfsr.routed_ncd_tracker
.................\....\...........\....\lfsr.twr
.................\....\...........\....\lfsr.twx
.................\....\...........\....\lfsr.ut
.................\....\...........\....\lfsr.xpi
.................\....\...........\....\lfsr_last_par.ncd
.................\....\...........\....\lfsr_map.ncd
.................\....\...........\....\lfsr_map.ngm
.................\....\...........\....\lfsr_pad.csv
.................\....\...........\....\lfsr_pad.txt
.................\....\...........\....\_impact.cmd
.................\....\...........\....\_impact.log
.................\..