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Title: RTL Download
 Description: Usb device on the control of nuclear ip has been redesigned and further optimize
 Downloaders recently: [More information of uploader shaqiu14550]
  • [usb_xilinx_vhdl] - usb-source _xilinx_vhdl This is a Xilinx
  • [USB_VHDL_coding] - USB2.0 the VHDL description, very classi
  • [usbfree_core] - Complete usb freecore, all prepared with
  • [uip-1.0] - UIP complete protocol stack, can be appl
  • [usb10] - usb1.0 discription
  • [vhdl] - usb rtl code, to fpga or asic
  • [slaveController] - On the USB device from the IP core has b
  • [USB] - Prepared with the VHDL source code to ac
File list (Check if you may need any files):
RTL
...\buffers
...\.......\dpMem_dc.v
...\.......\fifoRTL.v
...\.......\RxFifo.v
...\.......\RxFifoBI.v
...\.......\transcript
...\.......\TxFifo.v
...\.......\TxFifoBI.v
...\busInterface
...\............\wishBoneBI.v
...\hostController
...\..............\directcontrol.asf
...\..............\directcontrol.v
...\..............\getpacket.asf
...\..............\getpacket.v
...\..............\hctxportarbiter.asf
...\..............\hctxportarbiter.v
...\..............\hostcontroller.asf
...\..............\hostcontroller.v
...\..............\rxStatusMonitor.v
...\..............\sendpacket.asf
...\..............\sendpacket.v
...\..............\sendpacketarbiter.asf
...\..............\sendpacketarbiter.v
...\..............\sendpacketcheckpreamble.asf
...\..............\sendpacketcheckpreamble.v
...\..............\sofcontroller.asf
...\..............\sofcontroller.v
...\..............\softransmit.asf
...\..............\softransmit.v
...\..............\speedCtrlMux.v
...\..............\transcript
...\..............\usbHostControl.v
...\..............\USBHostControlBI.v
...\..............\work
...\..............\....\_info
...\hostSlaveMux
...\............\hostSlaveMux.v
...\............\hostSlaveMuxBI.v
...\include
...\.......\timescale.v
...\.......\usbConstants_h.v
...\.......\usbHostControl_h.v
...\.......\usbHostSlave_h.v
...\.......\usbSerialInterfaceEngine_h.v
...\.......\usbSlaveControl_h.v
...\.......\wishBoneBus_h.v
...\serialInterfaceEngine
...\.....................\lineControlUpdate.v
...\.....................\processRxBit.asf
...\.....................\processRxBit.v
...\.....................\processRxByte.asf
...\.....................\processRxByte.v
...\.....................\processTxByte.asf
...\.....................\processTxByte.v
...\.....................\readUSBWireData.v
...\.....................\siereceiver.asf
...\.....................\siereceiver.v
...\.....................\SIETransmitter.asf
...\.....................\SIETransmitter.v
...\.....................\updateCRC16.v
...\.....................\updateCRC5.v
...\.....................\usbSerialInterfaceEngine.v
...\.....................\usbTxWireArbiter.asf
...\.....................\usbTxWireArbiter.v
...\.....................\writeUSBWireData.v
...\slaveController
...\...............\endpMux.v
...\...............\fifoMux.v
...\...............\sctxportarbiter.asf
...\...............\sctxportarbiter.v
...\...............\slavecontroller.asf
...\...............\slavecontroller.v
...\...............\slaveDirectcontrol.asf
...\...............\slaveDirectcontrol.v
...\...............\slaveGetpacket.asf
...\...............\slaveGetpacket.v
...\...............\slaveRxStatusMonitor.v
...\...............\slaveSendpacket.asf
...\...............\slaveSendpacket.v
...\...............\transcript
...\...............\usbSlaveControl.v
...\...............\USBSlaveControlBI.v
...\...............\USBSlaveControlBI.v.bak
...\wrapper
...\.......\usbHost.v
...\.......\usbHostCyc2Wrap.v
...\.......\usbHostCyc2Wrap_usb1t11.v
...\.......\usbHostSlave.v
...\.......\usbHostSlaveAvalonWrap.v
...\.......\usbHostSlaveCyc2Wrap.v
...\.......\usbSlave.v
...\.......\usbSlaveCyc2Wrap.v
...\.......\usbSlaveCyc2Wrap_usb1t11.v
    

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