up_convert
..........\ddc.vhdl
..........\ddc.xml
..........\ddc_counter.vhdl
..........\ddc_tb.vhd.bak
..........\ddc_tb.vhdl
..........\ddc_tb.vhdl.bak
..........\modelsim.ini
..........\test.v
..........\test.v.bak
..........\work
..........\....\ddc
..........\....\...\duc_cos_arch.asm
..........\....\...\duc_cos_arch.dat
..........\....\...\_primary.dat
..........\....\ddc_counter
..........\....\...........\rtl.asm
..........\....\...........\rtl.dat
..........\....\...........\_primary.dat
..........\....\ddc_tb
..........\....\......\ddc_tb_arch.asm
..........\....\......\ddc_tb_arch.dat
..........\....\......\_primary.dat
..........\....\test
..........\....\....\verilog.asm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\_info