Description: cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
- [cordic_vhdl1] - use cordic achieve very Cartesian coordi
- [cordic.tar] - cordic procedures procedures VHDL source
- [magnitude] - Verilog HDL : For a vector magnitude (a,
- [FPGAusingall] - CPLD for all applications, so that spent
- [cordic_3] - Pipelined structure cordic, can output s
- [cordic_v1.0.4] - Altera
- [cordic] - cordic verilog simulation results proced
- [baseCORDIC] - CORDIC algorithm based on the design of
- [cordic] - CORDIC FPGA using the Verilog procedures
- [CORDIC_ATAN] - Verilog language used to complete based
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