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[Other resource] Viterbidecoder

Description: 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
Platform: | Size: 386457 | Author: 杨艺 | Hits:

[Other resource] viterbidecoder

Description: 提供实现了（2，1，7）卷积码的维特比译码的源程序，采用了最大似然算法，介绍了软判决维特比译码算法过程的三个步骤：初始化、度量更新和回溯译码。-for achieving a (2,1,7) Convolutional Codes Viterbi decoding of the source, using the maximum - likelihood algorithm, introduced a soft-decision Viterbi decoding algorithm of the three steps : initialization, Metric update and backtracking decoding.
Platform: | Size: 1261 | Author: 王雪松 | Hits:

[Communication] viterbidecoder

Description: 2，1，7卷积码的viterbi译码算法的FPGA实现，内容详细，而且附带源代码。
Platform: | Size: 1665189 | Author: Wayne | Hits:

[VHDL-FPGA-Verilog] Viterbidecoder

Description: 维特比解码器低功耗设计verilog编码完整的程序可直接用-Viterbi decoder low power design Verilog coding complete procedures can be used directly
Platform: | Size: 386048 | Author: 杨艺 | Hits:

[Communication-Mobile] Viterbi_Algorithm

Description: 卷积码的Viterbi译码算法仿真程序 要求：递归卷积码，归零处理-Convolutional Codes Viterbi decoding algorithm simulation program requirements : recursive convolutional codes and zeroing treatment
Platform: | Size: 3072 | Author: 牛兰奇 | Hits:

[DSP program] viterbidecoder

Description: 提供实现了（2，1，7）卷积码的维特比译码的源程序，采用了最大似然算法，介绍了软判决维特比译码算法过程的三个步骤：初始化、度量更新和回溯译码。-for achieving a (2,1,7) Convolutional Codes Viterbi decoding of the source, using the maximum- likelihood algorithm, introduced a soft-decision Viterbi decoding algorithm of the three steps : initialization, Metric update and backtracking decoding.
Platform: | Size: 1024 | Author: 王雪松 | Hits:

[Program doc] _2_1_7_viterbidecoder

Description: 基于MATLAB的2_1_7_维特比译码器的并行算法实现-MATLAB-based Viterbi decoder 2_1_7_ parallel algorithm
Platform: | Size: 311296 | Author: 罗青锋 | Hits:

[Communication] viterbidecoder

Description: 2，1，7卷积码的viterbi译码算法的FPGA实现，内容详细，而且附带源代码。-2,1,7 convolutional code of viterbi decoding algorithm realize the FPGA and detailed, but the source code attached.
Platform: | Size: 1665024 | Author: Wayne | Hits:

[Other] ViterbiDecoder

Description: 维特比译码，来自现代通信系统matlab-Viterbi Decoder, from modern communications systems matlab
Platform: | Size: 3072 | Author: 海之 | Hits:

[Communication-Mobile] ViterbiDecoder

Description: this a description viterbi decoder-this is a description viterbi decoder
Platform: | Size: 158720 | Author: Hossam Ahmed | Hits:

[ActiveX/DCOM/ATL] viterbidecoder

Description: viterbi decoder that use in communication
Platform: | Size: 2048 | Author: ali | Hits:

[Communication-Mobile] ViterbiDecoder

Description:
Platform: | Size: 379904 | Author: Krupesh | Hits:

[VHDL-FPGA-Verilog] viterbidecoder

Description: viterbi译码器的Verilog实现,(3,1,7)零尾卷积码-viterbi decoder implementation by verilog HDL （3，1，7）zero tail conventional code
Platform: | Size: 5120 | Author: zhouli | Hits:

[Books] Viterbidecoder

Description: 用VITEBI算法对信道输出解码。这个算法既能用于卷积码的软判决解码，也能用于硬判决解码-failed to translate
Platform: | Size: 2048 | Author: 李慧 | Hits:

[Windows Develop] viterbidecoder

Description: 移动通信系统中维特比译码器的硬件实现!j基于FPGA的有关编程代码-viterbi
Platform: | Size: 129024 | Author: 徐军 | Hits:

[CA auth] ViterbiDecoder

Description: Viterbi decode in VHDL
Platform: | Size: 5120 | Author: Lekha | Hits:

[Communication-Mobile] ViterbiDecoder

Description: 卷积码Viterbi译码，包括软判决和硬判决，别人上课的程序-Convolutional code Viterbi decoding, including soft decision and hard decision, others school programs
Platform: | Size: 54272 | Author: 郑鹏 | Hits:

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