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[MultiLanguage] VHDL-3fenpindianlu

Description: 该程序用VHDL硬件描述语言编写而成,已调试通过,程序运行后可实现三分频,这样就用软件设计代替了硬件设计,方便,稳定,不需要硬件调试!-the procedures used VHDL hardware description language, prepared debugging has passed, After running third frequency can be realized, so software designed to replace the hardware design, convenience, stability, no hardware debugging!
Platform: | Size: 2291 | Author: sdcsadf | Hits:

[VHDL-FPGA-Verilog] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309248 | Author: czy | Hits:

[JSP] 个用servlet实现购物车的程序

Description: 个用servlet实现购物车的程序,非常适合初学者学习，我也是初学者，看着这里这么多好的源代码，但是没有办法下载下来，只能说可惜了-use the servlet achieve Cart procedures, very suitable for beginners to learn, I also beginners Seeing so many good here source code, but not downloaded that can be said is a pity
Platform: | Size: 1024 | Author: woshijx | Hits:

[VHDL-FPGA-Verilog] 等精度频率计

Description: 使用vhdl语言写的fpga的应用程序，使献策内容为等精度频率计-use of the VHDL language they simply write the application procedures so that such ideas as to accuracy Cymometer
Platform: | Size: 251904 | Author: 丢丢熊 | Hits:

[ARM-PowerPC-ColdFire-MIPS] jtag_cpld_vhdl

Description: JTAG CPLD实现源代码，比用简单并口调试器快5倍以上。 以前总觉得简单的并口jtag板速度太慢，特别是调试bootloader的时候，简直难以忍受。最近没什么事情，于是补习了几天vhdl，用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15，晶振20兆，tck频率5兆。用sjf2410作测试，以前写50k的文件用时5分钟，现在则是50秒左右。tck的频率还可以加倍，但是不太稳定，而且速度的瓶颈已经不在tck这里，而在通讯上面了。 -JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: | Size: 2048 | Author: 李伟 | Hits:

[Other] washing

Description: 洗衣机控制器 做课程设计的同学可以下了看看 用vhdl语言做的 -washing machine controller design courses so students can see where the use of the VHDL language
Platform: | Size: 1024 | Author: 李莫普 | Hits:

[Button control] 4yue11haoxiawu

Description: 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the software and hardware design development (VB or V C and C language), downloading software and download Plate 3, Player (using Visual Basic 6.0 design) can play multiple formats of music and movies, Photo View and so on four small small inductance capacitor tester
Platform: | Size: 16384 | Author: wangxing | Hits:

[VHDL-FPGA-Verilog] ps2_soc2

Description: PS2的源代码VHDL语言实现，可以和计算机直接连接．做鼠标键盘接口．-PS2 source VHDL, and can be connected directly to the computer. So the mouse, keyboard interface.
Platform: | Size: 21504 | Author: 喻袁洲 | Hits:

[MPI] SPI-PRT

Description: 昨天在论坛上看到有人帖出了他写的并串转换VHDL代码，但是他自己说有问题，但是不知道怎么改。我大概看了一下，发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably watched and found ideas is quite a mess. So I wrote on their own code and string conversion.
Platform: | Size: 1024 | Author: ZHAOBOO | Hits:

[VHDL-FPGA-Verilog] HXRJTD

Description: 这是本人在Max plus2环境下用VHDL语言编的交通灯控制程序。做EDA课程设计的朋友可以下来参考参考。-This is my Max plus2 environment with VHDL addendum to the traffic lights control procedures. EDA design courses so friends from the reference reference.
Platform: | Size: 754688 | Author: 健 | Hits:

[assembly language] C51CrossLight

Description: 1.设计一个交通灯控制器。 2.利用学习机上的发光二极管，设定东、南、西、北4个方向，各3个灯（红、黄、绿）。交通灯控制器正常工作时，南北方向红灯亮3秒，黄灯闪2秒，绿灯亮3秒，以此类推。东西方向绿灯亮3秒，黄灯闪2秒，红灯亮3秒，以此类推。 3.设定两个紧急按钮，一个控制南北灯，一个控制东西灯。当按下相应的紧急键时，其控制方向的交通灯亮绿灯，其他方向的交通灯亮红灯，至自控键松开，恢复正常交通控制。 -1. Design of a traffic light controller. 2. Use of learning machine on the LED and set the East, South, West, North 4 direction, the three lights (red, yellow, green). Traffic signal controller normal working hours, the north- and south-bound red light three seconds, two seconds flashing yellow light, green light-three seconds, and so on. East-west direction green three seconds, two seconds flashing yellow light, red light three seconds, and so on. 3. Set two emergency buttons, a north-south control lights, a light control things. When pressing the corresponding key emergency, its control the traffic lights green, the other direction, the traffic lights class. Key to loose control and restore normal traffic control.
Platform: | Size: 10240 | Author: wangpeng | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: VHDL程序集锦，很多有用程序，英文版其中有汉明码编译码，优先译码等等。-VHDL Collection procedures, many useful procedures, the English version of them hamming code encoding and decoding, the priority decoder and so on.
Platform: | Size: 168960 | Author: 萍果 | Hits:

[VHDL-FPGA-Verilog] vhdl-intermediate

Description: VHDL进阶，在VHDL初步的基础上，使读者进一步深入了解VHDL语言现象和语句规划的特点，以及应用VHDL表达与设计电路的方法。-Advanced VHDL in VHDL preliminary basis, so that readers further insight into the phenomenon of VHDL language and expressions of the characteristics of planning, as well as the expression and application of VHDL circuit design approach.
Platform: | Size: 404480 | Author: 李芸 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机码发生器的VHDL实现 随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: vhdl的很多例子，包括LED、lcd、按键、数码管等等，非常的实用。-VHDL of many examples, including the LED, lcd, keypad, digital control and so on, very practical.
Platform: | Size: 855040 | Author: 盐城 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。 直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Platform: | Size: 37888 | Author: 袁玉佳 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 由于在网上很难下载到EDA技术－窦衡的PPT，所以本人经过学习后做成word，供大家下载。只针对VHDL语言部分和所有的程序。-Because the Internet is difficult to download to EDA technology- Douheng of the PPT, so I made after learning after the word, for all to download. Only for part of the VHDL language and all the procedures.
Platform: | Size: 2547712 | Author: 陈叶飞 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 利用VHDL实现任意函数发生器，包括方波、正弦波、三角波等。-The use of VHDL to achieve arbitrary function generator, including square, sine wave, triangle wave and so on.
Platform: | Size: 39936 | Author: 陈海巍 | Hits:

[VHDL-FPGA-Verilog] VHDL-dianti

Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示（设为A数）。 3梯运行的楼层数可自动显示（设为B数）。 4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升； 当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降； 当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门； 5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。 注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Platform: | Size: 34816 | Author: | Hits:

[VHDL-FPGA-Verilog] 用vhdl写实用96例子

Description: 用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)
Platform: | Size: 17153024 | Author: 朱朱8 | Hits:
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