Location:
Search - vhdl ip s
Search list
Description: VHDL中IP核之参数化加减法器中文使用介绍-VHDL IP parameters of the nuclear modified instruments used on the use of Chinese
Platform: |
Size: 146432 |
Author: 孙彬 |
Hits:
Description: 这是用vhdl语言写8051单片机的文档和程序.-vhdl This is the language used to write 8051's files and procedures.
Platform: |
Size: 5111808 |
Author: 李伟 |
Hits:
Description: 128点fft的IP核vhdl源代码,另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: |
Size: 7168 |
Author: 戈立军 |
Hits:
Description: spi接口的vhdl实现,所用器件和ip为xilinx的-spi interface VHDL realize, by ip for Xilinx devices and the
Platform: |
Size: 3112960 |
Author: 杨子树 |
Hits:
Description: VHDL版的C8051核(C8051).evatronix公司的IP核-VHDL version of the C8051 core (C8051). Evatronix company s IP core
Platform: |
Size: 739328 |
Author: |
Hits:
Description: 8051的IP,采用VHDL语言描述,支持intel的HEX格式,包括中断,定时器等.-8051 IP, the use of VHDL language description, support intel s HEX format, including the interruption, such as timers.
Platform: |
Size: 1021952 |
Author: 陈 |
Hits:
Description: alter公司的mcu核,8051ip核,为quartus2设计,其他应该兼容
-alter the company' s mcu nuclear, 8051ip nuclear, for quartus2 design should be compatible with other
Platform: |
Size: 9170944 |
Author: cvdsf |
Hits:
Description: VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.-VHDL IP Stack: This IP stack for an FPGA is a complex design because of the number of layers and the complexity of each that is required. It is limited to 10Mb/s operation and is designed for a full duplex switched network. It implements the lower layers of a standard TCP/IP stack. Further implementation is needed to make it work specifically for a certain purpose (eg a web server). There is support to read and write to RAM from the PC via the parallel port as well, for debugging and tests purposes (this maybe easily removed). Note the design only supports IP and ARP frames, other protocols such as RARP and 802.2 frames are not supported.
Platform: |
Size: 81920 |
Author: James |
Hits:
Description: usb 2.1 IP 的 东西 很好的 是 我的 -usb2.1 IP it s so eay to me to you
Platform: |
Size: 215040 |
Author: 电话 |
Hits:
Description: verilog实现的FFT变换,经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
Platform: |
Size: 618496 |
Author: culun |
Hits:
Description: 基于VHDL的SD卡IP核,Altera公司推出的大学计划!最新版本9.0-VHDL-based IP core of the SD card, Altera' s university program launched! The latest version 9.0
Platform: |
Size: 264192 |
Author: 兔子 |
Hits:
Description: 从opencore找都的ARM的IP CORE。有详细说明。-From opencore to find all of the ARM' s IP CORE. Is described in detail.
Platform: |
Size: 763904 |
Author: 老牛 |
Hits:
Description: simple AC97 Controller IP core. It supports one AC97 codec, with 6
output and 3 input channels.
This AC97 Controller s fully AC97 Revision 2.2 compliant. it only supports
AC97 Audio Codecs.
Platform: |
Size: 93184 |
Author: Gopi |
Hits:
Description: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s,需要再外扩一个PHY。-This is a USB 2.0 compliant core,USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Platform: |
Size: 196608 |
Author: liang |
Hits:
Description: 这是ALDEC公司的8255IP core,是用VHDL 语言写的,包括文档和代码-This is a ALDEC the company' s 8255IP core, is written in VHDL language, including the documentation and code
Platform: |
Size: 755712 |
Author: Zack |
Hits:
Description: 经典spi IP 核心 FPGA是实现有说明文档-spi IP based on fpga
Platform: |
Size: 49152 |
Author: wuyou |
Hits:
Description: 基于xilinx FPGA软核microblaze编写的PWM波产生IP核,在EXCD开发板上调试通过,内附UCF文件和说明-it s an IP core based on microblaze,it can produce pwm wave.
Platform: |
Size: 17408 |
Author: JK |
Hits:
Description: 2008-2009年优秀硕士论文之:基于FPGA的高性能32位浮点FFT IP核的开发-Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development
Platform: |
Size: 19145728 |
Author: dawei |
Hits:
Description: 关于千兆以太网的硕士论文,一边的mac层,一边是ahb总线slave接口。写的非常好。-Master s thesis on Gigabit Ethernet, while the mac layer, one side is ahb bus slave interface. Write very well.
Platform: |
Size: 1324032 |
Author: einstein |
Hits:
Description: XILINX 的IP核CAN V3.2的VHDL程序(XILINX's IP core: CAN_V3.2-VHDL)
Platform: |
Size: 45056 |
Author: sczzcxl |
Hits: