Description: This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
- [USBSpec20] - USB 2.0 agreement. USB 2.0 agreement on
- [USB2.0IP_core_Verilog] - complete with verilog language developme
- [usb20_ipcore_usb_funct] - usb chips ip core. with HDL description
- [USB] - Use VHDL to achieve USB IP core, we can
- [usb_phy.tar] - Very simple USB 1.1 PHY. Includes all th
- [vh2sc] - VH2SC is a free basic VHDL to SystemC co
- [802.11_PHY_PLCP] - Implemention for sublayer PLCP of PHY in
- [usb_funct] - usb2.1 IP it s so eay to me to you
- [verilog] - source code for USB 2.0 fonction core in
- [ST72681] - U disk drive chip USB 2.0 interface comp
File list (Check if you may need any files):
52135786usb_latest.tar
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