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[VHDL-FPGA-Verilog] FIRvhdl

Description: 用vhdl实现一个fir滤波器 设计要求： 1．最小阻带衰减-30db。 2．带内波动小于1db． 3．用MATLIB与MAXPLUS2联合设计与仿真-use VHDL to achieve a fir filter design requirements : 1. The smallest stop band attenuation- 30dB. 2. With fluctuating within less than 1DB. 3. With MATLIB with MAXPLUS2 joint design and simulation
Platform: | Size: 3072 | Author: 达闻西 | Hits:

[VHDL-FPGA-Verilog] fir_filter

Description: 常系数的FIR滤波器VHDL设计文件，在MUX+plusII调试通过-regular FIR filter coefficients of VHDL design documents, the debugging through MUX plusII
Platform: | Size: 3072 | Author: li | Hits:

[Button control] 4yue11haoxiawu

Description: 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the software and hardware design development (VB or V C and C language), downloading software and download Plate 3, Player (using Visual Basic 6.0 design) can play multiple formats of music and movies, Photo View and so on four small small inductance capacitor tester
Platform: | Size: 16384 | Author: wangxing | Hits:

[Other] motorctrl

Description: 滤波器设计及数据采集系统，希望对你有用，欢迎分享。本人想要VHDL的步进电机控制代码-filter design and data acquisition systems in the hope that useful to you, welcome to share. I want VHDL code stepper motor control
Platform: | Size: 251904 | Author: 代松洮 | Hits:

[VHDL-FPGA-Verilog] autofir

Description: 自适应滤波器设计的仿真程序，完全用C语言编写，可以作为滤波器设计的参考。原为VHDL实验要求的程序。-adaptive filter design simulation program, complete with C language can be used as filter design reference. VHDL to the original requirements of the experimental procedures.
Platform: | Size: 70656 | Author: 李博宁 | Hits:

[VHDL-FPGA-Verilog] CICFPGA

Description: 本文总结了CIC 滤波器理论要点，介绍了采用FPGA设计CIC 滤波器的基本方法，使滤波器的参数可以按实际需要任意更改，给出了仿真结，验证了设计的可靠性和可行性。采用该方法设计的CIC 滤波器已用于DDC芯片，也适合下一代高频雷达系统的要求。-This paper summarizes the main points of CIC filter theory, introduced the CIC filter design using FPGA basic ways in which filter parameters can be arbitrary according to the actual needs change, the simulation node to verify the reliability of the design and feasibility. Designed using the CIC filter has been used in DDC chips, also suitable for the next generation of high-frequency radar system requirements.
Platform: | Size: 700416 | Author: 会飞的鱼 | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 里面是一个FIR滤波器的设计报告 里面有具体的 代码 等等 加法器 乘法器 见发起 等等 承平-There is a FIR filter design report there are specific code adder multiplier, etc., etc., see Cheng-Ping initiated
Platform: | Size: 189440 | Author: 丛宇 | Hits:

[VHDL-FPGA-Verilog] DIGTAL_FIR

Description: 环路滤波器的设计，基于FPGA的锁相环应用。-Loop filter design, FPGA-based PLL applications.
Platform: | Size: 774144 | Author: 梁大法 | Hits:

[Documents] fir

Description: 线性相位FIR滤波器（17阶）的VHDL语言设计 功能很强大，很好用-Linear phase FIR filter (17 bands) of the VHDL language design features a very powerful, very good use
Platform: | Size: 148480 | Author: jingjing | Hits:

[VHDL-FPGA-Verilog] Filter

Description: vhdl抗抖动滤波器的设计，包括完整的工程-VHDL anti-jitter filter design, including the complete works
Platform: | Size: 256000 | Author: wanyou2345 | Hits:

[Software Engineering] bandpass-filter

Description: 这是一篇关于带通滤波器的毕业设计论文，涵盖IIR与FIR滤波器的设计！-This is an article on the band-pass filter design graduate thesis, covering IIR and FIR filter design!
Platform: | Size: 1155072 | Author: yuming | Hits:

[Communication-Mobile] filter

Description: 时钟滤波器设计，可进行毛刺去除，有需要可依进行参考设计-Clock filter design can be carried out burr removed, there is a need-based reference design
Platform: | Size: 2048 | Author: lee | Hits:

[VHDL-FPGA-Verilog] hbf

Description: 半带插值滤波器设计、综合、仿真和硬件测试-Half-band interpolation filter design, synthesis, simulation and hardware test
Platform: | Size: 18432 | Author: pll | Hits:

[Other] filter

Description: 滤波器的概念阐述，及一些常用的设计方法，主要用在数字系统中-Explained the concept of filters, and some commonly used design methods, mainly used in digital systems
Platform: | Size: 178176 | Author: li | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: FIR滤波器的性能参数 设计一个滤波器最基本的就是性能参数的,决定着滤波器的实际功能.比如阶数,截至频率。 本文滤波器设计参数 ①输入,输出数据宽度10位 ②阶数为4阶的线性相位FIR滤波器， ③类型:带通 -FIR filter performance parameters The design of a filter is the most basic performance parameters, determines the actual filter function. For example, the order, as the frequency. In this paper, filter design parameters ① input and output data width of 10 ② order for the 4 order of the linear phase FIR filter, ③ Type: Band Pass
Platform: | Size: 3072 | Author: bobo | Hits:

[VHDL-FPGA-Verilog] FIR_filters_Xilinx

Description: FIR filter design method using Xilinx FPGA platform.
Platform: | Size: 1805312 | Author: neorome | Hits:

[VHDL-FPGA-Verilog] FIR

Description: fir filter design using vhdl codes
Platform: | Size: 1024 | Author: gowtham | Hits:

[VHDL-FPGA-Verilog] IIR(vhdl)

Description: 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
Platform: | Size: 7168 | Author: sunnyhp | Hits:

[VHDL-FPGA-Verilog] 26352153-VHDL-Coding-for-FIR-Filter

Description: VHDL filter design powerpoint
Platform: | Size: 560128 | Author: HIDIR | Hits:

[VHDL-FPGA-Verilog] fir-filter-design-with-VHDL.doc

Description: 用VHDL设计一个18阶fir低通滤波器文档(VHDL design with a fir-order low-pass filter 18 documents)
Platform: | Size: 5120 | Author: sherry wang | Hits:
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