Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M Platform: |
Size: 776642 |
Author:张涛 |
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Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M Platform: |
Size: 776192 |
Author:张涛 |
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Description: ddr_sdram控制器的vhdl代码,里面的地址和数据长度可配置,能满足不同用户的需要.-ddr_sdram controller vhdl code, which addresses and the data length can be configured, meet the needs of different users. Platform: |
Size: 13312 |
Author:hxwf801 |
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Description: 一个使用VHDL设计的具有强大功能的32位CPU,这个文件包含了与之配套的DDR控制器程序!-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program! Platform: |
Size: 752640 |
Author:zhao onely |
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Description: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules Platform: |
Size: 1688576 |
Author:li ji wei |
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Description:
基于VHDL编写的DDR-SDRAM控制器的编程,目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller Platform: |
Size: 1031168 |
Author:wfs |
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Description: 这个设计是使用Virtex-4实现DDR的控制器的,设计分为三个主要模块:Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module. Platform: |
Size: 477184 |
Author:fdasfds |
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Description: 包含图像采集、i2c设计及混合语言仿真、DDR控制器以及一些小程序,供学习使用-Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use Platform: |
Size: 7177216 |
Author:陈少华 |
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Description: DDR controller source code and test bench in VerilogHDL. It is very useful to develop DDR project.-DDR controller source code and test bench in VerilogHDL. Platform: |
Size: 4096 |
Author:leos |
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Description: DDR2控制器设计原码,可以在FPGA上测试通过,并对外部的ddr memory进行读写访问.-DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access. Platform: |
Size: 52224 |
Author:yanxp |
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