DDRSDRAMControllerverilogcode This design is the u

Title: DDRSDRAMControllerverilogcode

Category:
VHDL-FPGA-Verilog
Tags:
[PDF]
File Size:
466kb
Update:
2012-11-26
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Uploaded by:
sheng.xue.fei

Description: This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.

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To Search: DDR DDR SDRAM DDR Controller sdram controller mpeg vhdl

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File list (Check if you may need any files):

DDRSDRAMControllerverilogcode
.............................\mem_interface_top.v
.............................\mem_interface_top_addr_gen_0.v
.............................\mem_interface_top_backend_fifos_0.v
.............................\mem_interface_top_backend_rom_0.v
.............................\mem_interface_top_cmp_rd_data_0.v
.............................\mem_interface_top_controller_iobs_0.v
.............................\mem_interface_top_data_gen_16.v
.............................\mem_interface_top_data_path_0.v
.............................\mem_interface_top_data_path_iobs_0.v
.............................\mem_interface_top_data_tap_inc.v
.............................\mem_interface_top_data_write_0.v
.............................\mem_interface_top_ddr_controller_0.v
.............................\mem_interface_top_idelay_ctrl.v
.............................\mem_interface_top_infrastructure.v
.............................\mem_interface_top_infrastructure_iobs_0.v
.............................\mem_interface_top_iobs_0.v
.............................\mem_interface_top_main_0.v
.............................\mem_interface_top_parameters_0.v
.............................\mem_interface_top_pattern_compare8.v
.............................\mem_interface_top_RAM_D_0.v
.............................\mem_interface_top_rd_data_0.v
.............................\mem_interface_top_rd_data_fifo_0.v
.............................\mem_interface_top_rd_wr_addr_fifo_0.v
.............................\mem_interface_top_tap_ctrl_0.v
.............................\mem_interface_top_tap_logic_0.v
.............................\mem_interface_top_test_bench_0.v
.............................\mem_interface_top_top_0.v
.............................\mem_interface_top_user_interface_0.v
.............................\mem_interface_top_v4_dm_iob.v
.............................\mem_interface_top_v4_dqs_iob.v
.............................\mem_interface_top_v4_dq_iob.v
.............................\mem_interface_top_wr_data_fifo_16.v
.............................\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.doc
.............................\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf

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