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[VHDL-FPGA-Verilog] FFT的VHDL源代码

Description: FFT的VHDL源代码-fft vhdl source code
Platform: | Size: 29696 | Author: 阿林 | Hits:

[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[Picture Viewer] 256VGA

Description: 256色图形开发包,支持3D建模 贴有3D模型效果图-256-color graphics development kits, 3D modeling support affixed with a 3D model Drawings
Platform: | Size: 747520 | Author: 阿林 | Hits:

[VHDL-FPGA-Verilog] fftmatlab

Description: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 7168 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker

Description: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL/Verilog simulator for CAD F PGA, board and IC design.
Platform: | Size: 292864 | Author: 陈亨利 | Hits:

[VHDL-FPGA-Verilog] ps2_vhdl

Description: 利用vhdl实现FPGA芯片从PS2键盘读出数据(0-F) 并在数码管上显示 -use FPGA chip from the PS2 keyboard sensed data (0-F) and displayed on a digital control
Platform: | Size: 1024 | Author: 刘音 | Hits:

[VHDL-FPGA-Verilog] TLC5510

Description: altera Quartus II TLC晶片控制 可控制暫存器，手動調整內碼。 (含電路) -altera Quartus II TLC chip control registers can be controlled manually adjust the code. (With circuit)
Platform: | Size: 129024 | Author: 陳小龍 | Hits:

[VHDL-FPGA-Verilog] FFT_VHDL

Description: FFT的VHDL源文件，经过在Quartus II上的测试无错误-FFT of the VHDL source file, after the Quartus II on the test error
Platform: | Size: 28672 | Author: 沈克镇 | Hits:

[Communication] 4cheng4jianpanxianshi

Description: 4乘4键盘识别与显示程序和说明（vhdl） 设计了一个的4x4键盘识别与显示模块。小键盘中有0~f共16个按键，小键盘和数码管都连接到PLD芯片上。-4 x 4 keyboard and display identification and description of procedures (vhdl) designed a recognition of the 4x4 keypad and display module. Small keyboard in the 0 ~ f total of 16 keys, small keyboard and digital tube are connected to the PLD chip.
Platform: | Size: 88064 | Author: coolrainy | Hits:

[VHDL-FPGA-Verilog] alu

Description: 4bit ALU（运算逻辑单元）的设计 给出了此次设计alu的输入输出结构及相应的位数。其中C0是一位的进位输入，A和B分别是4位的数据输入，S0、S1、M分别为一位的功能选择输入信号；Cout是一位的进位输出，F是4为的运算结果输出。-4bit ALU (arithmetic logic unit) design is given in the design of alu input and output structure and the corresponding median. C0 which is a binary input of, A and B are four data entry, S0, S1, M, respectively, as a function of choice of the input signal Cout of a binary output, F is 4 for computing the results of output.
Platform: | Size: 1024 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] seg

Description: 自己做的开发板，基于epm7064slc44-10控制数码管显示0-F。有助于初学者学习。-To do their own development board, based on the control epm7064slc44-10 digital tube display 0-F. Help beginners to learn.
Platform: | Size: 228352 | Author: 杨少栋 | Hits:

[VHDL-FPGA-Verilog] work3CNT4BDECL7S

Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
Platform: | Size: 82944 | Author: lkiwood | Hits:

[VHDL-FPGA-Verilog] FFT_VHDL

Description: FFT的FPGA实现里面有测试程序。希望对FPGA的学习朋友有所帮助！-FFT of the FPGA test procedure to achieve there. FPGA want to be helpful to learn a friend!
Platform: | Size: 437248 | Author: 夏浪 | Hits:

[VHDL-FPGA-Verilog] vhdlfft4

Description: 基4算法的vhdl实现，蝶形变换等的详细设计-Radix-4 algorithm of VHDL realize, butterfly transform the detailed design, etc.
Platform: | Size: 12288 | Author: 邓翔 | Hits:

[Embeded-SCM Develop] serial

Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --制器，10个bit是1位起始位，8个数据位，1个结束 --位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 --划分为8个时隙以使通信同步. --程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome" --字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制 --数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at - PC machine on the installation of a serial debugging tools to verify the function of the procedure. - Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control - System, and 10 bit is a start bit, 8 data bits, 1 Ending - Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real - Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are - 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time - Is divided into eight time slots in order to enable synchronous communication. - Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome" - String (serial debug tools is set to accept by way of A
Platform: | Size: 65536 | Author: johnson | Hits:

[VHDL-FPGA-Verilog] niosII_cyclone_1c20

Description: IIR、F FT各模块程序设计例程，可做为IP使用，初学者很有用-IIR, FIR, FFT modular design of the routines can be used as IP use, useful for beginners
Platform: | Size: 70656 | Author: 石林 | Hits:

[VHDL-FPGA-Verilog] B(f)

Description: 自己编的VHDL的波形发生器 做信号的可以-BOXING
Platform: | Size: 5120 | Author: WEI | Hits:

[Books] dds

Description: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Platform: | Size: 1442816 | Author: 王勤 | Hits:

[SCM] scan_LED

Description: 1） 输入设备为4*4矩阵键盘，分别代表0~F； 2） 输出设备为四位数码显示管，初始值显示0000，当按下某一键时，最右边的一位数码显示管显示最新一次所按按键的数值，而之前的显示值左移，例如，第一次按‘1’键，则显示0001；第二次按‘3’键，则显示0013；第三次按‘5’键，则显示0135；第四次按‘7’键，则显示1357；第五次按‘9’键，则显示3579，第四次按‘F’键，则显示579F-1) input device for the 4* 4 matrix keyboard, representing 0 ~ F 2) output device for the four digital display tubes, showed that the initial value of 0000, when the press of a button, it is the right of possession of a digital display according to the latest show by the numerical keys, and left before the display value, for example, the first time by the' 1 ' key, it shows 0001 the second time by the' 3' key, it shows 0013 the third time in accordance with' 5 ' button, it shows 0135 the fourth time by the' 7 ' key, it shows 1357 the fifth time by the' 9' key, it shows 3579, the fourth time by the ' F' keys, and so showed 579F
Platform: | Size: 199680 | Author: 王广玉 | Hits:

[Other] f

Description: This documents describes a free single precision floating point unit. This floating point unit can perform add, subtract, multiply, divide, integer to floating point and floating point to integer conversion.-This documents describes a free single precision floating point unit. This floating point unit can perform add, subtract, multiply, divide, integer to floating point and floating point to integer conversion.
Platform: | Size: 73728 | Author: k | Hits:
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