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[SourceCode] 实用verilog代码（乘法器，触发器,FIFO等）

Description: 本文件包含一些实用verilog程序代码，包括乘法器，除法器，伽罗瓦域乘法器，CORDIC数字计算机的设计，异步FIFO设计，伪随机序列应用设计，RS(204,188)译码器的设计，都是可综合的。对研究这部分的朋友有一定的帮助。
Platform: | Size: 28867 | Author: zhanxin0319 | Hits:

[VHDL-FPGA-Verilog] verilog乘法器设计

Description: verilog乘法器设计
Platform: | Size: 2349 | Author: liang2088321 | Hits:

[VHDL-FPGA-Verilog] codeofvhdl2006

Description: 【经典设计】VHDL源代码下载～～ 其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】 基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】 - [ Classics design ] the VHDL source code downloads ~ ~ classics the design to include: [ Vending machine ], [ electron clock ], [ traffic light traffic signal system ], [ step of 杩涚數 machine localization control system ], [ direct current machine speed control system ], [ calculator ], [ array LED display control system ] the basic numeral logical design includes: [ Latch ], [ multichannel selector ], [ 涓夋
Platform: | Size: 44032 | Author: senkong | Hits:

[VHDL-FPGA-Verilog] multiple

Description: 介绍了几种常用的乘法器的设计，carry_save_mult，ripple_carry_mult等，压缩包中包含结构流程图，用verilogHDL语言，采用modelsim仿真验证-This paper introduces some commonly used multiplier design, carry_save_mult, ripple_carry_mult such as, compressed package that contains the structure of flow chart, using verilogHDL language, using ModelSim simulation
Platform: | Size: 266240 | Author: yaoyongshi | Hits:

[VHDL-FPGA-Verilog] 64

Description: 64位乘法器，超前进位的，大家看看，通过仿真的，verilog的-64-bit multiplier, bit-ahead, let us look at the adoption of simulation, verilog of
Platform: | Size: 37888 | Author: | Hits:

[Books] 32bits_float_muliplier

Description: 32位浮点乘法器的设计，讲的挺好的，供参考啊-32-bit floating-point multiplier design, speak very good, and for reference ah
Platform: | Size: 97280 | Author: downloader | Hits:

[VHDL-FPGA-Verilog] mul_booth

Description: 基于BOOTH的32位快速乘法器的设计源码-BOOTH-based 32-bit fast multiplier design source
Platform: | Size: 2048 | Author: df | Hits:

[VHDL-FPGA-Verilog] c16_multiple

Description: 精通verilog HDL语言编程源码之2--常用乘法器设计-Proficient in verilog HDL source language programming of 2- Common Multiplier
Platform: | Size: 2048 | Author: 李平 | Hits:

[VHDL-FPGA-Verilog] c17_GF_multiple

Description: 精通verilog HDL语言编程源码之3--伽罗华域乘法器设计-Proficient in language programming verilog HDL source of 3- Galois field multiplier design
Platform: | Size: 1024 | Author: 李平 | Hits:

[VHDL-FPGA-Verilog] multiply

Description: Verilog hdl语言 常用乘法器设计，可使用modelsim进行仿真-Verilog hdl language commonly used multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] GFmultiply

Description: Verilog hdl语言 伽罗华域GF（q）乘法器设计，可使用modelsim进行仿真-Language Verilog hdl Galois field GF (q) multiplier design, can use the ModelSim simulation
Platform: | Size: 2048 | Author: 许立宾 | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[source in ebook] Chapter1-5

Description: 第一章到第五章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter to Chapter V of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, function authentication, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 1580032 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] 8bit_mult

Description: 八位快速乘法器设计verilog HDL-8 bit Fast Multiplier Designverilog HDL
Platform: | Size: 47104 | Author: 孙世玮 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作，又可完成子字并行操作模式，即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operations, but also to complete the sub-word parallel operation mode, that is, four 16bit* 16bit multiplication operation.
Platform: | Size: 99328 | Author: 余娅 | Hits:

[VHDL-FPGA-Verilog] mulx

Description: FPGA verilog乘法器 设计 用FPGA中DSP模块实现-FPGA verilog mulx
Platform: | Size: 544768 | Author: haziq | Hits:

[Open-source hardware] 常用乘法器设计

Description: 采用Verilog语言设计的几种常用乘法器。(several multiplier designed by verilog)
Platform: | Size: 2048 | Author: 熊猫松松 | Hits:

[VHDL-FPGA-Verilog] mul8

Description: 用verilog设计了一个两个8位二进制数的乘法器(A multiplier of two 8 bit binary numbers is designed with Verilog)
Platform: | Size: 17174528 | Author: vsslms | Hits:

[VHDL-FPGA-Verilog] GF乘法器

Description: 伽罗华域乘法器设计，包含了两个模块，设计较为简单(Galois field multiplier design, contains two modules, the design is relatively simple)
Platform: | Size: 1024 | Author: 未曾走远 | Hits:

[Other] 基于FPGA的单精度浮点数乘法器设计

Description: 《基于FPGA的单精度浮点数乘法器设计》详细介绍了按照IEEE754标准在FPGA上实现单精度浮点加减乘除的方法(The design of single precision floating point multiplier based on FPGA introduces in detail the way of realizing single precision floating point addition, subtraction and multiplication and division based on IEEE754 standard on FPGA.)
Platform: | Size: 2432000 | Author: sisuozheweilai | Hits:
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