Description: USB 设计（包括一个参考设计，和标准U盘）-USB design (including a reference design, and standards for U disk) Platform: |
Size: 546816 |
Author:zhangsan |
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Description: High volume USB 2.0 devices will be designed using ASIC technology with embedded USB 2.0 support.
For full-speed USB devices the operating frequency was low enough to allow data recovery to be handled
in a vendors VHDL code, with the ASIC vendor providing only a simple level translator to meet the USB
signaling requirements. Today s gate arrays operate comfortably between 30 and 60 MHz. With USB 2.0
signaling running at hundreds of MHz, the existing design methodology must change. Platform: |
Size: 342016 |
Author:rex |
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Description: ：CPLD 可编程技术具有功能集成度高、设计灵活、开发周期短、成本低等特
点。介绍基于ATMEL 公司的CPLD 芯片ATF1508AS 设计的串并转换和高速
USB 及其在高速高精度数据采集系统中的应用-: CPLD programmable technology with a high degree of functional integration, design flexibility, short development cycle, and low cost. ATMEL-based company introduced the CPLD chip ATF1508AS SERDES design and high-speed USB and its application in high-speed high-precision data acquisition system Platform: |
Size: 186368 |
Author:简单 |
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Description: 模拟网络串行通信 近期对计算机间通信比较感兴趣，同时研究usb通信原理，起步为串行通信于是想为更好地理解其机理做一定基础性研究，故做了异步串行通信设计实验。
经过QUARTUS验证，获得了一等奖！-Simulation of the recent serial communication network between the communication of more interested in computers, communications usb at the same time the principle of starting for serial communication therefore would like to better understand the mechanism to do some basic research, it has done the design of asynchronous serial communication experiment . After verification QUARTUS obtained the first prize! Platform: |
Size: 1860608 |
Author:ayls |
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Description: --- --- --- -Verilog--- --- ----
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog----------------
This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor.
Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize. Platform: |
Size: 168960 |
Author:Sami |
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Description: 基于FPGA的驱动设计，使得用户的USB驱动在此完美实现。-FPGA-based drive design makes the user' s USB drive in this work perfectly. Platform: |
Size: 770048 |
Author:liuyu |
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Description: 在高速的数据采集或传输中，目前使用较多的都是采用USB 2．0接口控制器和FPGA或DSP实现的，本设计在USB 2．0接口芯片CY7C68013的Slave FIFO模式下，利用FPGA作为外部主控制器实现对FX2 USB内部的FIFO进行控制，以实现数据的高速传输。该模块可普遍适用于基于USB 2．0接口的高速数据传输或采集中。-In the high-speed data acquisition or transmission, the currently used are based on more USB 2.0 interface controller and the FPGA or DSP implementation, the design USB 2.0 interface chip CY7C68013 of the Slave FIFO mode, the use of FPGA as a the external FX2 USB host controller to realize the internal FIFO control, in order to achieve high-speed data transmission. The module can be generally applied based on high-speed USB 2.0 interface, transfer or acquisition of data. Platform: |
Size: 894976 |
Author:jiang_jennifer |
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Description: 在FPGA外扩用FT2232 实现UART TO USB 2.0 的通信。-The FT2232H is a USB2.0 Hi-Speed USB Device to FIFO IC.
This core allows the use of this chip with an FGPA design in high speed FT245 style synchronous FIFO mode.
Data rates up to 25 mbytes/s can be achieved. The core has internal FIFOs on the receive and transmit for improved throughput.
For more information see FTDI s appnote "AN_130_FT2232H_Used_In_FT245 Synchronous FIFO Mode.pdf"
Included: VHDL core, NIOS test application, PC test application
Platform: |
Size: 6144 |
Author:李涛 |
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Description: The design is designed partly in VHDL, partly in schematic drawings and targets a Xilinx Spartan-2E FPGA. However, since the design was tailored specifically for the aforementioned boards it is highly unlikely that it can be ported to other hardware. The circuits were designed on a Windows XP using the Xilinx WebPack 6.2 tool. The transfer of the design to the FPGA was carried out either with the Xilinx Impact tool through a parallel JTAG cable or with the Digilent Export utility through a USB JTAG cable. Platform: |
Size: 1854464 |
Author:sami |
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Description: USB1.1标准接口的IP核的实现和其设计实现的源码范例VHDL-USB1.1 standard interface IP core implementations and examples of their design and implementation of the VHDL source code Platform: |
Size: 425984 |
Author:sxhfjgl010 |
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