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Description: 一个简单功能的对话框制作的秒表,主要应用MFC的ontimer计时器函数-A simple function of the dialog box produced by a stopwatch, the main applications of the MFC timer function ontimer
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Size: 1926144 |
Author: 姜明威 |
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Description: 显示99秒的秒表功能 有proteus的图 和源代码-Show the 99 seconds of the stopwatch function Proteus plans and source code
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Size: 91136 |
Author: 王涵 |
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Description: 给出了数字跑表的源代码,设计了分频模块,实现了真实的时间计数,通过这个工程的训练,能更好的了解Quartus II数字电路开发的过程。-Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quartus II development of the process of digital circuits.
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Size: 237568 |
Author: 张应辉 |
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Description: matlab GUI中 实时显示钟表时间的用户操作界面-matlab GUI real-time clocks, time display user interface
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Size: 2048 |
Author: 毛飞 |
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Description: 99秒马表,单片机8051经典源码之一,看后对你的汇编大有帮助-99 seconds stopwatch, Microcontroller 8051, one of the classic source, see you after the compilation of great help
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Size: 2048 |
Author: michael |
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Description: 000-999跑表 STC89C52单片机 + 数码管显示-000-999 stopwatch STC89C52 Singlechip+ Digital tube display
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Size: 1024 |
Author: 辛坤 |
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Description: 文通过ALTERA公司的quartus II软件,用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为:计时功能,24小时制计时显示;通过七段数码管动态显示时间;校时设置功能,可分别设置时、分、秒;跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
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Size: 182272 |
Author: 张保平 |
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Description: 基于fpga的停表设计vudl编写,使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
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Size: 1024 |
Author: youngbing |
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Description: Proteus + KeilC 开发的跑表程序。简单、完整,适合初学者参考。-Proteus+ KeilC development stopwatch procedure. Easy, complete, suitable for beginners reference.
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Size: 46080 |
Author: test0731 |
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Description: 包含若干个VHDL小例子,有交通灯,电子琴,简易秒表,等等,交通灯已经测试过,根据自己的需要,稍微改动,很好用!-VHDL contains a number of small example, there is traffic lights, Electronic organ, simple stopwatch, and so on, traffic lights have been tested, according to their own needs, slightly altered, very good use!
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Size: 327680 |
Author: lee gilbert |
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Description: 基于FPGA的秒表设计 基于FPGA的秒表设计-FPGA-based FPGA design is based on the stopwatch stopwatch stopwatch design FPGA-based design
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Size: 478208 |
Author: shmyg |
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Description: moto a1200 stopwatch
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Size: 97280 |
Author: 许亚 |
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Description: 一个基于FPGA的数字跑表系统的设计,最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
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Size: 44032 |
Author: jyb |
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Description: 一个模拟现实世界的秒表,可以无限制地使用,你可以进行一次,也可以两次,三次等,按任意键开始,按任意键结束!-A simulation of the real world, stopwatch, you can open the doors to unrestricted use, once you can can also be twice, thrice and so on, press any key to start, press any key to end!
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Size: 43008 |
Author: 安树峰 |
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Description: 一个用VHDL编写的秒表程序,可用Max+PlusII仿真-Prepared by a stopwatch with VHDL procedures, Max+ PlusII simulation can be used
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Size: 620544 |
Author: jiangshengcheng |
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Description: 秒表实现暂停,继续,开始,并且带有同步的秒针显示,数字的精确到0.01-Stopwatch to achieve the suspension to continue, start, and synchronized with the second hand indicates that the precision of the figures to 0.01
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Size: 1024 |
Author: shenyi |
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Description: LPC2119,C语言,ADS1.2,用四个LED数码管实现秒表计时。-LPC2119, C language, ADS1.2, four LED digital tube stopwatch timing to achieve.
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Size: 66560 |
Author: 士大夫 |
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Description: eda实现的电子秒表,稳定,精确,适合eda实验参考程序-eda electronic stopwatch to achieve stable, accurate and suitable for experimental reference procedures eda
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Size: 350208 |
Author: pan |
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Description: 基于CPLD的VHDL语言数字钟(含秒表)设计
利用一块芯片完成除时钟源、按键、扬声器和显示器(数码管)之外的所有数字电路功能。所有数字逻辑功能都在CPLD器件上用VHDL语言实现。这样设计具有体积小、设计周期短(设计过程中即可实现时序仿真)、调试方便、故障率低、修改升级容易等特点。
本设计采用自顶向下、混合输入方式(原理图输入—顶层文件连接和VHDL语言输入—各模块程序设计)实现数字钟的设计、下载和调试。
-CPLD based on the VHDL language digital clock (with stopwatch) design using a chip can be completed in addition to the clock source, buttons, speakers and display (LED) in addition to all functions of digital circuits. All digital logic functions are used in the CPLD device VHDL language. This design has a small and short design cycle (design process to achieve timing simulation), to facilitate debugging, fault rate is low and easy to modify the characteristics of the upgrade. The design uses a top-down, mixed input (input schematic- top-level file access and VHDL language input- the module program design) Design of digital clock, download and debug.
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Size: 95232 |
Author: wuhuisong |
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Description: stopwatch matlab source code
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Size: 2048 |
Author: PSH |
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