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[VHDL-FPGA-Verilog] vhdl_vga

Description: 彩条信号发生器使用说明 使用模块有：VGA接口、脉冲沿模块、时钟源模块。 使用步骤： 1. 打开电源+5V 2. 信号连接，按下表将1K30信号与实际模块连接好。 3. 1K30板连接好并口线，并将程序加载。 4. 将彩色显示器的线与VGA接口连接好。 5. 彩条信号就可以在显示器中产生，通过脉冲沿模块按键MS1可以改变产生彩条的 -color of the signal generator for use with the use of modules : VGA, pulse along the module, module clock source. Use steps : 1. Turn the power 5V 2. Signal connectivity, the table below will 1K30 signal with the actual module linking well. 3. 1K30 good parallel plate connections and will be loading procedures. 4. Will the line color display with VGA interface connector good. 5. Choi of the signal can be generated in the display, along the pulse button MS1 module can change color of the produce
Platform: | Size: 95232 | Author: 刘浪 | Hits:

[VHDL-FPGA-Verilog] ntsc_gen

Description: NTSC信号发生器VHDL源码。输出为BT656格式-NTSC signal generator VHDL source code. BT656 format output
Platform: | Size: 1024 | Author: 吕奔 | Hits:

[matlab] Application_in_FPGA_design_of_Matlab_simulink

Description: 分析了MATLAB/Simulink 中DSP Builder 模块库在FPGA 设计中优点， 然后结合FSK 信号的产生原理，给出了如何利用DSP Builder 模块库建立FSK 信号发生器模 型，以及对FSK 信号发生器模型进行算法级仿真和生成VHDL 语言的方法，并在modelsim 中对FSK 信号发生器进行RTL 级仿真，最后介绍了在FPGA 芯片中实现FSK 信号发生器的设 计方法。-Analysis of the MATLAB/Simulink in DSP Builder Blockset in the FPGA design advantages, and then combined with the emergence of the principle of FSK signal is given how to use DSP Builder Blockset establish FSK signal generator model, as well as the FSK signal generator model algorithm class VHDL simulation and generation language approach, and in ModelSim for FSK signal generator for RTL-level simulation, and finally introduce the FPGA chip realize FSK signal generator design method.
Platform: | Size: 275456 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 伪随机码发生器的VHDL实现 随着通信理论的发展，早在20世纪40年代，香农就曾指出，在某些情况下，为了实现最有效的通信，应采用具有白噪声的统计特性的信号。另外，为了实现高可靠的保密通信，也希望利用随机噪声。然而，利用随机噪声最大困难是它难以重复产生和处理。直到60年代，伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

[VHDL-FPGA-Verilog] work5FREQTEST

Description: 8位十六进制频率计设计 根据频率的定义和频率测量的基本原理，测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号；1s计数结束后，计数值被锁入锁存器，计数器清零，为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器（FTCTRL）来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
Platform: | Size: 244736 | Author: lkiwood | Hits:

[VHDL-FPGA-Verilog] FPGA_signal_general

Description: 摘 要：介绍了直接数字频率合成 (DDS) 技术的基本原理，给出了基于Altera公司FPGA器件的一个三相正弦信号发生器的设计方案，同时给出了其软件程序和仿真结果。仿真结果表明：该方法生成的三相正弦信号具有对称性好、波形失真小、频率精度高等优点，且输出频率可调。 关键词：直接数字频率合成；现场可编程门阵列；FPGA；三相正弦信号-Abstract: Direct Digital Synthesis (DDS) technology, the basic principles are given Altera-based FPGA devices the company a three-phase sinusoidal signal generator design program, at the same time give its software programs and simulation results. The simulation results show that: the method to generate three-phase sinusoidal signal with good symmetry, waveform distortion small, the frequency of high precision, and adjustable output frequency. Key words: direct digital synthesizer field programmable gate array FPGA three-phase sinusoidal signal
Platform: | Size: 101376 | Author: 赵文 | Hits:

[VHDL-FPGA-Verilog] vhdldds0000

Description: 采用fpga的hdl语言实现dds的信号发生器的设计，性能与传统相比明显提高。-Hdl language using FPGA implementation of the signal generator dds design, performance markedly improved compared with the traditional.
Platform: | Size: 172032 | Author: 李江 | Hits:

[Software Engineering] DDS

Description: 本设计基于数字频率合成技术,采用正弦查找表实现波形产生.直接数字频率合成技术（DDS）是一种先进的电路结构，能在全数字下对输出信号频率进行精确而快速的控制，DDS技术还在解决输出信号频率增量选择方面具有很好的应用，DDS所产生的信号具有频率分辨率高、频率切换速度快、频率切换时相位连续、输出相位噪声低和可以产生任意波形等诸多优点。 文中介绍了DDS的基本原理，对DDS的质谱及其散杂抑制进行了分析。程序设计采用超高速硬件描述语言VHDL描述DDS,在此基础上设计了正弦波、三角波、方波等信号发生器，。完成了软件和硬件的设计，以及实验样机的部分调试。 -The design is based on a digital frequency synthesis technology, to achieve wave synthesis by sine wave look-up tables. Direct Digital Synthesis Technology (DDS) is an advanced circuit structure, the output signal frequency is controlled precisely and rapidly in all-digital process, DDS technology has been applied in output signal frequency increment. DDS signals generated own high frequency resolution, frequency switching speed and continuous phase when frequency switching, low-output phase noise and can generate arbitrary waveform, and so on. Basic principles of the DDS is introduced in the paper, frequency form and stray inhabitation of the DDS is analyzed. Procedures designed with high-speed hardware description language VHDL describe DDS, and design a sine wave, triangle wave, square-wave signal generator by it.The hardware and software has been designed, prototype and circuit has been tested partly.
Platform: | Size: 312320 | Author: 蓝 | Hits:

[Software Engineering] sji

Description: 频率合成技术在现代电子技术中具有重要的地位。在通信、雷达和导航等设备中，它可以作为干扰信号发生器；在测试设备中，可作为标准信号源，因此频率合成器被人们称为许多电子系统的“心脏”。直接数字频率合成（DDS——Digital Direct Frequency Synthesis）技术是一种全新的频率合成方法，是频率合成技术的一次革命。本文主要分析了DDS的基本原理及其输出频谱特点，并采用VHDL语言在FPGA上实现。对于DDS的输出频谱，一个较大的缺点是：输出杂散较大。针对这一缺点本文使用了两个方法加以解决。首先是压缩ROM查找表，-Abstract；The frequency synthesis technology has the important status in the modern electronic technology. In equipment such as correspondence, radar and navigation, it may work as the unwanted signal generator In the test facility, may work as the standard signal source, therefore the frequency synthesizer is called by the people as "the heart" of many electronic systems .DDS——Digital Direct Frequency Synthesis technology is one brand-new frequency synthetic method, is a frequency synthesis technology revolution. This paper analyzes the basic principle of DDS and its output frequency spectrum characteristic, and realizes it with VHDL language on FPGA. In regard to the output
Platform: | Size: 961536 | Author: 番薯军 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS信号发生器，利用VHDL实现，可根据频率控制字的改变输出不同频率的信号，最高可到达10MBPS-DDS signal generator, the use of VHDL realization of frequency control word in accordance with changes in output signals of different frequencies, the maximum arrival 10MBPS
Platform: | Size: 784384 | Author: 陈宇 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 包括用用VHDL语言编写的DDS,FIFO,交通控制灯，数字电压计，信号发生器的源码，希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
Platform: | Size: 69632 | Author: link | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 正弦信号发生器具有频率调节功能。采用VHDL编程实现。-Sinusoidal signal generator with a frequency adjustment function. Using VHDL programming.
Platform: | Size: 1482752 | Author: 朱广利 | Hits:

[Embeded-SCM Develop] zhenxianxinhao

Description: 此文件是正弦信号发生器实验的源码，这是老师的资料，对课堂很有帮助-This file is the sine signal generator with source code, it is the teacher of information helpful to the classroom
Platform: | Size: 1024 | Author: 董军 | Hits:

[VHDL-FPGA-Verilog] 6

Description: 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。 设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。 输入：连续脉冲，逻辑开关；输出：七段LED。 -4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously. Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output. Input: Continuous pulse, logic switches output: seven-segment LED.
Platform: | Size: 4096 | Author: 李小勇 | Hits:

[VHDL-FPGA-Verilog] interweave_1

Description: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data.
Platform: | Size: 36864 | Author: 李修函 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register with the state controller clk, the clock signal clk2 sent to the data controller and the state controller, the signal sent to fetch the data controller and address of the multiplexer, the signal sent to the arithmetic logic unit alu_clk.
Platform: | Size: 4096 | Author: cccs | Hits:

[VHDL-FPGA-Verilog] SG_FPGA

Description: 2006年电子设计竞赛二等奖，多功能函数、信号发生器核心器件FPGA内部的原理图，主要模块用VHDL代码描述，包括PLL、相位累加器、波形算法和正弦波查找表，可实现0.005Hz~20MHz的多波形信号产生，频率步进值0.005，输出接100MSPS速率的DAC--AD9762-Electronic Design Competition 2006, second prize, multi-function signal generator within the core of the device schematic FPGA, VHDL code with the description of the main modules, including the PLL, phase accumulator, sine lookup table algorithm and the waveform can be realized 0.005Hz ~ 20MHz multi-waveform signal generator, the frequency step value of 0.005, then the output rate of 100MSPS DAC- AD9762
Platform: | Size: 1099776 | Author: zlz | Hits:

[VHDL-FPGA-Verilog] signal-generator-base-on-vhdl

Description: 实现正弦波输出，可以调节输出频率，具有led显示功能-Achieve sine wave output, output frequency can be adjusted, with led display
Platform: | Size: 401408 | Author: 杨某 | Hits:

[VHDL-FPGA-Verilog] Multi-function-waveform-generator

Description: 本系统应用VHDL语言及MAX+PLUS II仿真软件利用自顶向下的设计思想进行设计，结合示波器加以完成一个可应用于数字系统开发或实验时做输入脉冲信号或基准脉冲信号用的信号发生器，它具结构紧凑，性能稳定，设计结构灵活，方便进行多功能组合的特点，经济实用，成本低廉。具有产生四种基本波形脉冲信号（方波、三角波、锯齿波和正弦波），且脉冲信号输出幅度及输出频率可调，对于方波信号，还可以实现占空比可调。通过软件仿真和硬件测试都得到了预期的结果。-The system using VHDL language and MAX+ PLUS II simulation software using a top-down design ideas to design a combined oscilloscope be completed to do the input pulse signal or reference pulse signal with the signal generator used in digital system development or experimentalwith compact structure, stable performance, flexible structure design, convenient multifunction portfolio characteristics, economical and practical, low cost. Has four basic waveform pulse signal (square wave, triangle wave, sawtooth and sine wave), and the amplitude of the pulse signal output and the output frequency is adjustable, adjustable duty cycle square wave signal can also be achieved. Expected results through software simulation and hardware testing.
Platform: | Size: 1485824 | Author: xinxing | Hits:

[Other] vhdl

Description: 用计数器、3/8译码器和门电路设计序列信号发生器用示波器观察并测量波形。-Counter, 3/8 decoder circuit design sequence and doors to observe and measure the waveform signal generator with an oscilloscope.
Platform: | Size: 1024 | Author: lailai | Hits:
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