Description: Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data.
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interweave_1
............\interweave_1
............\............\interweave_cording.vhd
............\............\interweave_decording.vhd
............\............\m_sequence.vhd
............\............\top_interweave.vhd
............\............\Waveform Editor top_interweave.awf
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