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[Other] SDR-SDRAM-ctl1

Description: SDR SDRAM控制器，FPGA vhdl代码-SDR SDRAM Controller
Platform: | Size: 718848 | Author: | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。 先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程 目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文件夹里面是仿真工程 \test_bench文件夹里面是测试文件 \wave文件夹里面是仿真波形 -Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Description: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
Platform: | Size: 779264 | Author: 军军 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: SDRAM驱动器，自己项目利用的，已经经过实际验证-sdram controller
Platform: | Size: 4096 | Author: 田云钧 | Hits:

[Other] ddr-sdram-verilog-resource

Description: 描述了ddr_sram的源代码,包括SDRAM的引脚功能介绍和Verilog在modulesim及quartus ii的实现-description the resource code of ddr_sram
Platform: | Size: 896000 | Author: wangyuzhuo | Hits:

[Software Engineering] SDRAM

Description: 连接Nios II 和SDRAM的系统设计，DDR SDRAM设计及调试经验总结，MT48LC16M16资料。-failed to translate
Platform: | Size: 1903616 | Author: luyi | Hits:

[Embeded Linux] SDRAM-HY57V641620

Description: SDRAM-HY57V641620中文资料-SDRAM-HY57V641620
Platform: | Size: 432128 | Author: paradise | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: SDRAM控制器，使用verilog编写-SDRAM controller, use the write verilog
Platform: | Size: 776192 | Author: yangbo | Hits:

[Other Embeded program] sdram

Description: TI TMS320 DM642 开发板 SDRAM测试工程-Test project of SDRAM module for DM642 EVM
Platform: | Size: 190464 | Author: 张超 | Hits:

[VHDL-FPGA-Verilog] ref-sdr-sdram-verilog

Description: sdram的verilog 建模参考设计，希望有所帮助-sdram and verilog implent
Platform: | Size: 886784 | Author: pengyong | Hits:

[VHDL-FPGA-Verilog] sdram-source

Description: SDR SDRAM 控制器的源代码 altera公司的-source code from altera
Platform: | Size: 717824 | Author: wela | Hits:

[DSP program] sdram

Description: DSP 和SDRAM读写程序 其中主函数用汇编编写。执行效率较高-DSP and SDRAM
Platform: | Size: 25600 | Author: 袁伟杰 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: how to use sdram ip ， just for fpga
Platform: | Size: 458752 | Author: baoyu | Hits:

[VHDL-FPGA-Verilog] sdram

Description: SDRAM ctrller 用于SDRAM控制器的读写控制，利用4个 FIFO实现读写数据的缓存。-sdram ctrl
Platform: | Size: 186368 | Author: 张朋 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 对SDRAM的介绍非常详细，里面有很多对SDRAM的程序控制模块的设计。-Very detailed presentation on the SDRAM, which has many of the SDRAM of the process control module.
Platform: | Size: 23523328 | Author: 魏大胜 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xxxx xxxx sdram 在 0044 0045 0046 处的数据； sdram 使用的是 K4S161622D.pdf 系统时钟 25m， 通过 PLL 得到 SDRAM clk 100m sdram controller clk 100m， 前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
Platform: | Size: 14336 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: SDRAM控制器，Verilog代码编写，让你快速了解SDRAM的读写时序。包含Modelsim仿真工程和学习笔记-SDRAM controller, Verilog coding, allows you to quickly understand the SDRAM read and write timing. Modelsim simulation engineering and contains study notes
Platform: | Size: 3031040 | Author: jianzi | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: FPGA SDRAM控制器Verilog源码，通过测试-FPGA SDRAM VERILOG
Platform: | Size: 5120 | Author: 大海 | Hits:

[VHDL-FPGA-Verilog] SDRAM-control

Description: SDRAM控制器的Verilog源代码，主要用于SDR-SDRAM-SDRAM controller
Platform: | Size: 2824192 | Author: 金文超 | Hits:

[VHDL-FPGA-Verilog] SDRAM-controller-design-FPGA-based

Description: 基于FPGA的SDRAM控制器设计及应用硕士论文-SDRAM controller design FPGA based
Platform: | Size: 3163136 | Author: connie | Hits:

[VHDL-FPGA-Verilog] SDRAM

Description: 介绍了sdram的原理，非常详细，可以供学习者和开发者参考-Introduced the principle of sdram, very detailed, you can reference for learners and developers
Platform: | Size: 1942528 | Author: 萤火之光 | Hits:
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