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[VHDL-FPGA-Verilog] Crack_QII8.0

Description: quartus 8 的内存注册机，已经试验过，非常好用，完全破解。-quartus 8 Zhuceji memory has been tested, very easy to use, completely broken.
Platform: | Size: 15360 | Author: 庄保国 | Hits:

[VHDL-FPGA-Verilog] Crack

Description: quartus ii 7.1 7.0crack
Platform: | Size: 583680 | Author: lmn3951 | Hits:

[Other] Crack_QII72

Description: QUARTUS-7.2的破解软件，可以破解QUARTUS-7.2，能用到2034年。-The crack QUARTUS-7.2 software, can crack QUARTUS-7.2, can be used to in 2034.
Platform: | Size: 337920 | Author: 苏洲 | Hits:

[VHDL-FPGA-Verilog] 4

Description: QUARTUS 的配置及调试 flv的 -Quartus flv configuration and commissioning of the
Platform: | Size: 2603008 | Author: ljc | Hits:

[VHDL-FPGA-Verilog] 5

Description: vhdl的仿真 quartus 2的flv视频 -VHDL simulation of the flv video quartus 2
Platform: | Size: 3582976 | Author: ljc | Hits:

[VHDL-FPGA-Verilog] DS1307_LCD

Description: 通过IIC总线读写实时时钟DS1307，并把时、分、秒显示在12864液晶屏上，用的CycloneII EP2C8，Quartus环境-Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
Platform: | Size: 1311744 | Author: iversn | Hits:

[matlab] matlab_quartus

Description: 可以方便地将matlab里的数据导入quartus中的波形仿真文件中，很有用-Matlab can easily import the data in waveform simulation Quartus document, very useful
Platform: | Size: 1024 | Author: 侯训平 | Hits:

[Linux-Unix] Quartusguide_huawei_pdf[1]

Description: quartus中文全部说明 可以方便初学者使用 改软件-Quartus Chinese full description can be easily changed to use software for beginners
Platform: | Size: 2458624 | Author: 薛少杰 | Hits:

[VHDL-FPGA-Verilog] stopwatch

Description: 秒表可计时，用VHDL编译的源代码，从0.1到60秒计时，解压后直接用Quartus打开project即可-Stopwatch timer can be used to compile the VHDL source code, from 0.1 to 60 seconds from time, after extracting the direct use of Quartus can open the project
Platform: | Size: 577536 | Author: xie | Hits:

[source in ebook] 200681556499797

Description: 曼彻斯特编解码 用vhdl编写的，经过quartus功能仿真测试过了的-Manchester codec prepared using VHDL, the Quartus functional simulation has been tested
Platform: | Size: 103424 | Author: yin | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 给出了数字跑表的源代码，设计了分频模块，实现了真实的时间计数，通过这个工程的训练，能更好的了解Quartus II数字电路开发的过程。-Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quartus II development of the process of digital circuits.
Platform: | Size: 237568 | Author: 张应辉 | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[Books] AnExperimentOfDE2_70

Description: 本文介绍的是一个具体的例子，给出了借助QUARTUS II 7.2和Nios II 7.2 IDE实现跑马灯实验的整个流程。-This article describes a specific example given by QUARTUS II 7.2 and Nios II 7.2 IDE Marquee experimental realization of the entire process.
Platform: | Size: 1060864 | Author: Wuxinmin | Hits:

[Other] TimeQuest_Basic

Description: Quartus里面的TimeQuartus资料-Quartus inside information TimeQuartus
Platform: | Size: 1035264 | Author: guoqiang | Hits:

[Other] CLOCK

Description: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止 、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Platform: | Size: 182272 | Author: 张保平 | Hits:

[Other] DSP

Description: 学习fpga/cpld的书籍，介绍quartus 2及dsp builder的使用，-Learning fpga/cpld books, introduced quartus 2 and dsp builder use,
Platform: | Size: 14001152 | Author: 彭武军 | Hits:

[VHDL-FPGA-Verilog] ff

Description: QUARTUS II平台上的基于VHDL语言的电梯系统控制程序。-QUARTUS II platform based on the VHDL language elevator system control procedures.
Platform: | Size: 259072 | Author: 凌丽 | Hits:

[VHDL-FPGA-Verilog] Execise

Description: altera官方网站上资料的示例代码Quartus II Software Design Series Foundation-altera official website information sample code Quartus II Software Design Series Foundation
Platform: | Size: 18641920 | Author: jiangwen | Hits:

[Other] Sinout

Description: dds正弦可控发生计全结果 用到matlab，dsp，Quartus II 6.0软件-dds controllable sinusoidal occurred wholly the result of use of matlab, dsp, Quartus II 6.0 software
Platform: | Size: 134144 | Author: linjun | Hits:

[VHDL-FPGA-Verilog] vga_timing

Description: 此乃VGA驱动的详细源码，并配有PLL。使用Quartus II 开发。-This is a detailed source VGA driver with a PLL. Use Quartus II development.
Platform: | Size: 253952 | Author: 荣俊齐 | Hits:
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