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[VHDL-FPGA-VerilogS3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731136 | Author: Roy Hsu | Hits:

[SCM006e405654b730e0857dfda923646ead

Description: Mihai Cucicea 描述:一人参加的迷宫游戏 Requires: D2SB and DIO4 with VGA monitor and PS2 Keyboard -Mihai Cucicea Description: First person to participate in the maze game Requires: D2SB and DIO4 with VGA monitor and PS2 Keyboard
Platform: | Size: 97280 | Author: wangwei | Hits:

[VHDL-FPGA-Verilogps2

Description: PS2接口的VHDL实现,希望对大家有帮助。-PS2 interface VHDL realize, in the hope that everyone has to help.
Platform: | Size: 7168 | Author: 张开文 | Hits:

[VHDL-FPGA-Verilogexample

Description: 几个基本的VHDL例子,包括VGA显示,鼠标键盘PS2接口,数码管等。在XILINX板子上均可运行-Several basic VHDL examples, including VGA display, mouse, PS2 keyboard interface, digital tubes, and so on. XILINX board may be in the running
Platform: | Size: 2675712 | Author: kljlj | Hits:

[VHDL-FPGA-VerilogPS2_verilog_source

Description: 在vhdl开发环境下,关于协议PS2 verilog 源码-In VHDL development environment, with regard to the agreement PS2 verilog source code
Platform: | Size: 1024 | Author: clwclwclw | Hits:

[VHDL-FPGA-Verilogps2

Description: ps2接口源程序。标准的键盘和鼠标接口,在Xilinx SpartanII XC2S200 实验板上通过验证-ps2 interface source. Standard keyboard and mouse interface, in the experiments on-board Xilinx SpartanII XC2S200 validated
Platform: | Size: 23552 | Author: Alex | Hits:

[VHDL-FPGA-VerilogS9_PS2_LCD

Description: 键盘输入液晶模块显示字符,在液晶显示屏上显示从PS2键盘输入的字符-Keyboard input LCD display module characters displayed in the LCD screen from the PS2 keyboard input characters
Platform: | Size: 765952 | Author: zl.yin | Hits:

[Windows Developlcd

Description: 使用PS2接口的键盘的小键盘输入,在12864液晶上显示出来,使用平台为CPLD或FPGA-PS2 keyboard interface to use a small keyboard input, in the 12864 liquid crystal display, use the platform for the CPLD or FPGA
Platform: | Size: 1053696 | Author: luojicheng | Hits:

[VHDL-FPGA-VerilogVHDL

Description: 8*8乘法器设计 伪随机序列发生器 PS2键盘设计 均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
Platform: | Size: 2048 | Author: qiumh | Hits:

[SCMDesktop

Description: it is the ps2 interface code writed in modelsim
Platform: | Size: 4096 | Author: om | Hits:

[VHDL-FPGA-VerilogPS2-Mouse

Description: ps2-mouse port in fpga board
Platform: | Size: 729088 | Author: stupidme | Hits:

[VHDL-FPGA-Verilogps2

Description: 采用sopc技术,nios2ide开发环境,实现nios对ps2键盘的控制,按键讲ascii码显示在led上-Using sopc technology, nios2ide development environment to achieve nios right ps2 keyboard control, key speakers led the ascii code is displayed in
Platform: | Size: 8153088 | Author: 蹇清平 | Hits:

[Driver Developkeyboard_vhdl

Description: ps2 keyboard with encoding ascii code to 7-segments screeen. LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY klawa IS PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC SW : in std_logic_vector(4 downto 0) HEX1, HEX2, HEX0, HEX3, HEX4, HEX5, HEX6, HEX7 : out std_logic_vector(6 downto 0) ) end klawa architecture Behavioral of klawa is component keyboard PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC scan_code : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) scan_ready : OUT STD_LOGIC ) END component -ps2 keyboard with encoding ascii code to 7-segments screeen. LIBRARY ieee USE ieee.std_logic_1164.all USE ieee.std_logic_arith.all USE ieee.std_logic_unsigned.all ENTITY klawa IS PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC SW : in std_logic_vector(4 downto 0) HEX1, HEX2, HEX0, HEX3, HEX4, HEX5, HEX6, HEX7 : out std_logic_vector(6 downto 0) ) end klawa architecture Behavioral of klawa is component keyboard PORT ( keyboard_clk, keyboard_data, clock_25MHz,reset,read1 : IN STD_LOGIC scan_code : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) scan_ready : OUT STD_LOGIC ) END component
Platform: | Size: 637952 | Author: arekk | Hits:

[VHDL-FPGA-Verilogps_2_keyboard

Description: 用VHDL语言编写的ps2键盘程序,可以在de2实验板上运行。初学者适用-VHDL language with the ps2 keyboard program, you can experiment in the de2 board to run. For beginners
Platform: | Size: 1049600 | Author: dingxing | Hits:

[VHDL-FPGA-VerilogPS2

Description: 应用VHDL编写的基于FPGA的PS2键盘程序-Applications written in VHDL FPGA-based procedures for PS2 keyboard
Platform: | Size: 262144 | Author: 紫云 | Hits:

[VHDL-FPGA-VerilogISE_lab19

Description: 基于VHDL语言编写的俄罗斯方块游戏,由VGA接口和电脑显示器显示,用PS2键盘操作控制。-Written in VHDL-based Tetris game, by the VGA interface and a computer display, with a PS2 keyboard control.
Platform: | Size: 3850240 | Author: 大机子 | Hits:

[VHDL-FPGA-Verilogps2

Description: 除了顶层模块(ps2_key),三个底层模块分别为PS/2传输处理模块(ps2scan)、串口传输模块(my_uart_tx)以及串口波特率选择模块(speed_select)(下面只给出顶层模块和PS/2传输处理模块的verilog代码,串口部分的设计可以参考串口通信设计)。-In addition to top-level module (ps2_key), three low-level modules are PS/2 transmission processing module (ps2scan), serial transmission module (my_uart_tx) and the serial port baud rate selection module (speed_select) (the following is given only to top-level module and PS/2 verilog code for transport processing module, serial part of the design can refer to the serial communication design).
Platform: | Size: 155648 | Author: lishaohui | Hits:

[VHDL-FPGA-Verilogps2-keyboard

Description: PS2 KEYBIARD interfacing with lcd 2X16-PS2 KEYBIARD interfacing with lcd 2X16
Platform: | Size: 1689600 | Author: mahdi | Hits:

[VHDL-FPGA-Verilogfpga_dk_ps2_vga

Description: ps2 vga interface in vhdl code
Platform: | Size: 2948096 | Author: frostmourne089 | Hits:

[Software EngineeringSpecifiche-Mouse-PS2

Description: PS/2 Mouse Specifications (ITA): this pdf explains how to interface a standard PS/2 mouse to a custom logic system, for example a FPGA system described in VHDL.
Platform: | Size: 507904 | Author: Lorenzo | Hits:
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