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[Software EngineeringVHDL_PLL

Description: 介绍了锁相环PLL的实现原理,可以为VHDL实现PLL提供参考。-introduced PLL PLL The principle for VHDL PLL reference.
Platform: | Size: 96256 | Author: CGT | Hits:

[Communication-Mobilemy_pll

Description: VHDL程序,使用锁相法实现位同步的算法,并可以对算法进行仿真-VHDL, the use of lock-in-law to achieve the synchronization algorithm, the algorithm can be simulated
Platform: | Size: 1024 | Author: 笑容 | Hits:

[Communication-MobileEXPT12_10_PHAS_PLL1

Description: VHDL 实现DDS的数字移相信号发生器的设计代码.直接解压打开就可以运行..自己写的代码-VHDL shifter DDS signal generator design code. Directly extract can run on open .. write their own code
Platform: | Size: 119808 | Author: haiou | Hits:

[VHDL-FPGA-VerilogPLL

Description: PLL 时钟模块  Quartus II平台的简单设计实例 附仿真波形-PLL clock module Quartus II platform attached to a simple design example simulation waveforms
Platform: | Size: 806912 | Author: 许东滨 | Hits:

[VHDL-FPGA-VerilogADI_pll_Set

Description: VHDL编写的ADI锁相环控制程序,可以调试ADI锁相环的相关系列十几个型号。引脚命名和锁相环相关控制引脚对应。-VHDL prepared ADI PLL control procedures, you can debug ADI PLL related series more than a dozen models. Pin naming and PLL control pin for the corresponding correlation.
Platform: | Size: 1024 | Author: M | Hits:

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