Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - phase detector verilog

Search list

[Other resource] 1_061115131201

Description: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
Platform: | Size: 9056 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] 1_061115131201

Description: 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
Platform: | Size: 9216 | Author: mingming | Hits:

[Other] chA

Description: phase frequency detector verilog
Platform: | Size: 13312 | Author: kdlee | Hits:

[3G develop] Verilog_module

Description: Verilog编写基于FPGA的鉴相器模块-Write Verilog FPGA-based phase detector module
Platform: | Size: 457728 | Author: zhh | Hits:

[Algorithm] cordic_atan

Description: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
Platform: | Size: 79872 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
Platform: | Size: 668672 | Author: 栾帅 | Hits:

[VHDL-FPGA-Verilog] phase_test

Description: 基于verilog的鉴相器设计，鉴相器是锁相环的一部分，功能是检测两个时钟是否同步-The phase detector based on verilog design, PLL phase detector is part of function is to test whether the two clock synchronization
Platform: | Size: 1024 | Author: 林锋 | Hits:

[VHDL-FPGA-Verilog] costas

Description: costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
Platform: | Size: 6144 | Author: 潇潇 | Hits:

[VHDL-FPGA-Verilog] VPD__using_FFe

Description: verilog开发一种种基于fpga的鉴相器模块 -the verilog development of all kinds based on fpga phase detector module
Platform: | Size: 447488 | Author: 房产 | Hits:

[Other] Verilog-Code

Description: Verilog source code by James Patchell: - Delta Sigma Modulator for doing Digital->Analog Conversion - Aquad-bquad phase detector - Uart Reciever - Uart Transmitter - One shot
Platform: | Size: 7168 | Author: happyuser | Hits:

[VHDL-FPGA-Verilog] dpll

Description: 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider
Platform: | Size: 6144 | Author: chi zhang | Hits:

CodeBus www.codebus.net