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Description: modelsim破解工具安装modelsim后运行它即可破解-modelsim crackers after installation modelsim run it can break
Platform: | Size: 228352 | Author: 苏醒 | Hits:

[VHDL-FPGA-Verilog] hamin0132

Description: 汉明码的编结码模块，用verilog写成，为Modelsim下的一个工程。-series guitar code modules, using Verilog languages, as Modelsim of a project.
Platform: | Size: 31744 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] QPSK2154

Description: QPSK的VERLOG源码，在MODELSIM下的一个工程，有测试向量。-QPSK VERLOG source of the MODELSIM of a project, test vector.
Platform: | Size: 23552 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] dll11254

Description: 数字琐相环DPLL的VERLOG代码，MODELSIM下的工程，有测试文件-digital phase-locked loop DPLL VERLOG code MODELSIM under the projects, a test document
Platform: | Size: 19456 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] crc3321

Description: CRC循环校验码的VERILOG源文件，在MODELSIM下的一个工程。-Cyclic Check Code VERILOG source, the MODELSIM of a project.
Platform: | Size: 26624 | Author: 刘仪 | Hits:

[VHDL-FPGA-Verilog] parity2258

Description: 奇偶校验码的VERILOG源码，为MODELSIM下的一个工程。有测试文件。-parity VERILOG source code for MODELSIM of a project. A test document.
Platform: | Size: 25600 | Author: 刘仪 | Hits:

Description: 第一节 ispDesignEXPERT 简介第二节 ispDesignEXPERT System 的原理图输入第三节设计的编译与仿真第四节 ABEL 语言和原理图混合输入第五节 ispDesignEXPERT System 中 VHDL 和Verilog 语言的设计方法第六节在系统编程的操作方法第七节 ModelSim 的使用方法附录一 ispDesignEXPERT System 上机实习题附录二 ispDesignEXPERT System 文件后缀及其含义-Introduction Section II, section I ispDesignEXPERT ispDesignEXPE RT System III schematic design input to the compilation and simulation fourth ABEL language and schematics mixed input System V ispDesignEXPERT VHDL and Verilog language the statement in section VI Design System Programming methods of operation of the sect ModelSim use is an appendix pDesignEXPERT System attachment that the plane Appendix 2 ispDesignEXPE RT System file extension and its meaning
Platform: | Size: 1292288 | Author: 吴忌 | Hits:

[VHDL-FPGA-Verilog] wavefetch

Description: ModelSim的波形比较的功能可以将当前仿真与一个参考数据（WLF文件）进行比较，比较的结果可以在波形窗口或者列表窗口中查看，也可以将比较的结果生成一个文本文件-ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the waveform window or window List View, it will also compare the results generate a text file
Platform: | Size: 3072 | Author: cyberworm | Hits:

[Other] Modelsim_How_to_use_pdf

Description: ML Modelsim教程（PDF）.zip-ML Modelsim Guide (PDF). Zip
Platform: | Size: 732160 | Author: 申平 | Hits:

[VHDL-FPGA-Verilog] firmatlab

Description: fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] sinmdlmatlab

Description: 正弦波在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-sine wave in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker

Description: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL/Verilog simulator for CAD F PGA, board and IC design.
Platform: | Size: 292864 | Author: 陈亨利 | Hits:

[VHDL-FPGA-Verilog] shift_register_testbench

Description: 16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
Platform: | Size: 23552 | Author: yeqing | Hits:

[VHDL-FPGA-Verilog] FFT_CORE

Description: FFT算法的VHDL语言实现可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
Platform: | Size: 29696 | Author: 紫蓝 | Hits:

[VHDL-FPGA-Verilog] SPI_verilogHDL

Description: 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success in the compiler, Modelsim SE with six successful simulation.
Platform: | Size: 1024 | Author: jevidyang | Hits:

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[Other] Keygen

[VHDL-FPGA-Verilog] hamin0132

[VHDL-FPGA-Verilog] QPSK2154

[VHDL-FPGA-Verilog] dll11254

[VHDL-FPGA-Verilog] crc3321

[VHDL-FPGA-Verilog] parity2258

[Books] ispDesignExpert

[VHDL-FPGA-Verilog] wavefetch

[Other] Modelsim_How_to_use_pdf

[VHDL-FPGA-Verilog] firmatlab

[VHDL-FPGA-Verilog] sinmdlmatlab

[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker

[VHDL-FPGA-Verilog] shift_register_testbench

[VHDL-FPGA-Verilog] FFT_CORE

[VHDL-FPGA-Verilog] SPI_verilogHDL

[VHDL-FPGA-Verilog] pwm_higt

[VHDL-FPGA-Verilog] hdb3_verilog

[VHDL-FPGA-Verilog] ModelSim_TestBench_VHDL

[Program doc] ModelSim_SE_tigeress359617728

[VHDL-FPGA-Verilog] ModelSim_foundation

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