Search - modelsim

[VHDL-FPGA-Verilog] adc8888

Description: 8位的a/d行为模型，可以应用于modelsim等环境下的仿真，不可综合。-eight of the a/d behavior model can be applied to other environments modelsim the simulation, not comprehensive.
Platform: | Size: 2048 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] sram__

Description: 静态随机读取存储器行为模型，可以应用于modelsim环境的仿真。-static random acts of reading memory model can be applied to the simulation environment modelsim.
Platform: | Size: 2048 | Author: 江浩 | Hits:

[VHDL-FPGA-Verilog] oem_man

Description: Modelsim使用教程，英文版，从新建工程到完成仿真讲的非常详细，适合初学者。-Modelsim use guides, in English, from new construction to be completed simulation in a very detailed, for beginners.
Platform: | Size: 2044928 | Author: snake | Hits:

[VHDL-FPGA-Verilog] modelsim_guide_cn

Description: modelsim操作指导很适合入门有实例-modelsim operation guidance is very suitable example of a portal
Platform: | Size: 342016 | Author: 大师 | Hits:

[VHDL-FPGA-Verilog] fulleradder

Description: 本程序以Modelsim为开发平台，采用VHDL为开发语言，实现了简单的全加器．适合初学Modelsim的同行-Modelsim the procedures for the development of a platform for the development of VHDL language, achieving a simple full adder. Suitable for a novice counterparts Modelsim
Platform: | Size: 30720 | Author: 刘小军 | Hits:

[VHDL-FPGA-Verilog] modelsim_userguide

Description: 仿真软件MODELSIM的用户使用手册，对MODELSIM用户有很大帮助。-MODELSIM simulation software users manuals, MODELSIM users to be of much help.
Platform: | Size: 3899392 | Author: liujie | Hits:

[VHDL-FPGA-Verilog] Freq_counter

Description: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Platform: | Size: 515072 | Author: 许的开 | Hits:

[Software Engineering] Modelsim_houfangzhen

Description: this is a book of modelsim hou fang zhen,it is very good for study modelsim,-this is a book of modelsim hou fang zhen, it is very good for study modelsim.
Platform: | Size: 429056 | Author: 王明 | Hits:

[VHDL-FPGA-Verilog] RISCMCU

Description: riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
Platform: | Size: 594944 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] CPUNEW

Description: MODELSIM开发的模拟CPU，用VHDL语言描述，采用累加结构-ModelSim simulation developed CPU, using VHDL language description of the structure of the use of cumulative
Platform: | Size: 50176 | Author: yyy | Hits:

[VHDL-FPGA-Verilog] vhdlYONGHUSHOUCE

Description: 非常优秀的国外VHDL设计教程，可进行MODELSIM模拟等操作-Excellent foreign VHDL design tutorial, it can conduct operations such as ModelSim Simulation
Platform: | Size: 2766848 | Author: yyy | Hits:

[VHDL-FPGA-Verilog] Fir

Description: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 1024 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] 4VerilogFIFO

Description: 一种新的FIFO实现方法,verilog描述，通过modelsim 6.0 仿真，Quartue综合-FIFO realize a new method, verilog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 2048 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] 89_full_adder

Description: full adder设计代码，verilog 语言描述，通过modelsim 仿真，quartus综合-full adder design code, verilog language to describe, through the ModelSim simulation, quartus integrated
Platform: | Size: 4096 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] Modelsim_timing_simulation_library

Description: 文章论述如何将向modelsim中添加仿真库，包括添加xilinx,altera,actel公司的仿真库的方法-Article on how to add ModelSim simulation library, including the add xilinx, altera, actel the company
Platform: | Size: 114688 | Author: zhurui | Hits:

[VHDL-FPGA-Verilog] modelsim6.0

Description: 使用說明對於modelsim的如何操作和使用及安裝的如何安裝-ModelSim for use of how to operate and use and installation of how to install
Platform: | Size: 388096 | Author: kkk | Hits:

[VHDL-FPGA-Verilog] DSP_BUILDER_DESIGN

Description: DSP Builder设计初步,介绍Matlab/DSP Builder及其设计流程，正弦信号发生器完整的设计过程，以及使用Matlab、quartusII\modelsim详细的仿真过程。-DSP Builder preliminary design, introduce Matlab/DSP Builder and its design flow, sinusoidal signal generator complete design process, and the use of Matlab, quartusIImodelsim detailed simulation.
Platform: | Size: 1370112 | Author: yehui | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list