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Description: 波特率发生器的设计，这里是实现上述功能的VHDL源程序，供大家学习和讨论。
-baud rate generator design, here is the realization of the above-mentioned functional VHDL source code for all learning and discussion.
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Size: 3072 |
Author: 许嘉 |
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Description: pwm s generator for direct torque control of induction motor-PWM generator for direct torque control o f induction motor
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Size: 1024 |
Author: 冉嘉奇 |
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Description: JLex词法分析生成器，可以用于生成简单词法分析器，java编写-JLex lexical analysis generator can be used to produce simple lexical analyzer, the preparation of java
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Size: 94208 |
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Description: VB实现的注册码发生器 ，为制作共享软件提供帮助-VB The license generator, the production-sharing software to help
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Size: 137216 |
Author: wflee |
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Description: FSK信号发生器,用于软件测试.采样率、波特率，幅度，f1，f2可调，不含wave头，样点类型I16，保存为文件-FSK signal generator for software testing. Sampling rate, baud rate, magnitude, f1, f2 adjustable, excluding the first wave, point-like type infarction, preservation of documents
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Size: 420864 |
Author: pengsophy |
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Description: 单个脉冲发生器的multisim9仿真文件-single pulse generator simulation document multisim9
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Size: 282624 |
Author: 欧阳菲菲 |
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Description: 本程序应用了混沌序列作为伪码生成器对直接扩频系统进行了仿真，并在多用户情况下作了仿真-the application procedures as a chaotic sequence of pseudo-code generator directly to the spread spectrum system simulation, Multi-user and the circumstances made Simulation
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Size: 8192 |
Author: 王也 |
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Description: 正弦波信号发生器
1、摘要：使用查表法在屏幕上显示正弦波信号。
2、参考资料：
IBM-PC汇编语言程序设计（第二版）
Intel汇编语言程序设计（第四版）
(汇编语言）-a sine wave signal generator, Abstract : Checking displayed on the screen sine wave signal. 2, reference materials : IBM-PC Assembly Language Programming (2nd edition) Intel assembly language programming (fourth edition) (Compendium language)
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Size: 11264 |
Author: 孙锋志 |
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Description: 此文件采用了verilog语言在cpld中怎样实现波形发生器，及其验证程序-this document using the Verilog language in the cpld How to achieve waveform generator, and the verification process
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Size: 4096 |
Author: liu |
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Description: 电力系统在台稳定计算式电力系统不正常运行方式的一种计算。它的任务是已知电力系统某一正常运行状态和受到某种扰动，计算电力系统所有发电机能否同步运行
1运行说明：
请输入初始功率S0，形如a+bi
请输入无限大系统母线电压V0
请输入系统等值电抗矩阵B
矩阵B有以下元素组成的行矩阵
1正常运行时的系统直轴等值电抗Xd
2故障运行时的系统直轴等值电抗X d
3故障切除后的系统直轴等值电抗
请输入惯性时间常数Tj
请输入时段数N
请输入哪个时段发生故障Ni
请输入每时段间隔的时间dt-power system stability in the Taiwan Power computing system is not the normal operating mode of calculation. Its mission is a known power system uptime status and be subject to some disturbance, computing power system all synchronous generator can run an operation Note : Please enter the initial power S0, shaped like a bi Please enter the infinite system bus voltage V0 Please enter the system equivalent reactance matrix B matrix B group has the following elements the line matrix into a normal operation of the system straight axis equivalent reactance Xd two fault systems running straight axis equivalent reactance X d 3 after resection of the fault system straight axis equivalent reactance Please enter the inertial time constant Tj Please enter the number of hours which N Please enter a tim
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Size: 1024 |
Author: 魏鹏 |
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Description: dds信号发生器-dds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, FSK
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Size: 3331072 |
Author: appolo |
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Description: 等腰三角波发生器，在simulink 中有的是锯齿波和三角波的现成模块，可是等腰三角波的就没有了，现提供给大家。-isosceles triangular wave generator, which in some Simulink ramp and triangular wave off-the-shelf modules, But isosceles triangle wave, there is no, it is available to everyone.
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Size: 3072 |
Author: 王丽 |
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Description: § Debussy有四個主要單元(component)，nTrace、nWave、nSchema、nState
§ nTrace -- Hypertext source code analysis and browse tool (為％Debussy &所開啟的主畫面)
§ nWave -- Waveform analysis tool (可由nTrace內開啟，或直接％nWave &開啟)
§ nSchema -- Hierarchy schematic generator
-§ Debussy has four main modules (component), nTrace, nWave, nSchema, nState § nTrace- Hypertext source code analysis and browse tool (as Debussy
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Size: 3695616 |
Author: frankyq |
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Description: 正弦信号发生器[2005年电子大赛一等奖].files-sinusoidal signal generator [e-Competition in 2005 won first prize]. Files
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Size: 113664 |
Author: sadfa |
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Description: IP流量发生器，用于产生UDP报文，该程序用于模拟你需要的IP流量。可运行于Linux-IP flow generator, used to produce UDP packet, the procedure you need to simulate the IP flow. Can be run on Linux
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Size: 1024 |
Author: Rex Yan |
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Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。
-the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
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Size: 784384 |
Author: 东子 |
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Description: 用matalab开发的随机数生成程序包，用于各种随机数的生成，可到以下网址更新和浏览详细的说明：http://www.math.uu.se/research/telecom/software/-matalab development with the random number generator package, for various random number generator. can be updated to the following website and browse detailed explanation : http :// www.math.uu.se/research/telecom/softwa 're /
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Size: 62464 |
Author: 王邦新 |
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Description: The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification. -The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.
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Size: 9935872 |
Author: Jawen |
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Description: 基于单片机的函数信号发生器. 51单片机，双0832-based SCM function signal generator. 51 microprocessor, double 0832
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Size: 45056 |
Author: 55 |
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Description: UML不是一种程序设计语言,但我们可以用代码生成器将UML模型转换为多种程序设计语言代码,或使用反向生成器工具将程序源代码转换为UML模型
此模型正是 UML设计建模的一个实例：图书馆信息系统希望有兴趣的朋友下载
-UML is not a programming language, However, we can use the code generator to UML model conversion for a wide range of programming language code, or the use of reverse generator tool source code into UML model is the model design UML is a modeling cases : Library Information System hope friends are interested in downloading
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Size: 23552 |
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