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[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[DSP program] 电子线路实验报告

Description: 设计一数字 频率计，其技术要求如下： (1) 测量频率范围：1Hz~100kHz。 (2) 准确度Dfx/fx£ ± 2%。 (3) 测量信号：方波，峰峰值为3V~5V。-design a figure frequency meter, the technical requirements are as follows : (a) measuring frequency range : 1Hz- 100kHz. (2) the accuracy Dfx/fxpound 2%. (3) Measurement of signal : square wave peak to peak for 3V to 5V.
Platform: | Size: 86016 | Author: 兰 | Hits:

[SCM] MSP430F133频率计程序

Description: 这是一个基于MSP430F133的频率计程序-This is a based on the frequency meter MSP430F133 procedures
Platform: | Size: 1024 | Author: lsl | Hits:

[Other Embeded program] freq

Description: 一个基于quartus2的等精度频率计的设计，主要采用的verilogＨＤＬ语言-Based on the quartus2 such as a precision frequency meter design, the main language used in verilogHDL
Platform: | Size: 481280 | Author: 张新 | Hits:

[Other Embeded program] Freq

Description: 简易数字频率计，用Verilog HDL编写的，基于Quartus II实现，结构清晰，功能较为全面，能满足简单的频率测量要求-Simple digital frequency meter, using Verilog HDL prepared, based on the Quartus II realize, clear structure, function is more comprehensive to meet the simple requirements of frequency measurement
Platform: | Size: 404480 | Author: 余翔 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: VERILOG设计实例，非常详细的例子，有交通灯，频率计，数字跑表等等例子-Verilog design example, a very detailed examples have traffic lights, frequency meter, digital stopwatch, etc. Examples of
Platform: | Size: 159744 | Author: luojinwen | Hits:

[VHDL-FPGA-Verilog] counter

Description: verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
Platform: | Size: 145408 | Author: chen | Hits:

[VHDL-FPGA-Verilog] gate_control

Description: verilog写的数字频率计的控制模块,对程序进行控制-written in Verilog digital frequency meter control module, the program control
Platform: | Size: 97280 | Author: chen | Hits:

[VHDL-FPGA-Verilog] dispselect

Description: verilog写的数字频率计的选择模块,用与显示的选择-written in Verilog digital frequency meter option module, used and display options
Platform: | Size: 82944 | Author: chen | Hits:

[VHDL-FPGA-Verilog] 4weishuzipinlvjikongzhimokuai

Description: Verilog HDL下的4 位数字频率计控制模块源代码-Verilog HDL under four digital frequency meter control module source code
Platform: | Size: 3072 | Author: 李少洋 | Hits:

[Software Engineering] fre_ctrl

Description: 利用verilog语言，从上至下层次管理的设计思想；Verilog HDL的行为描述和结构描述,实现8位频率计，4个0检测修正电路的原理说明-The use of Verilog language, top-down hierarchical management design idea Verilog HDL description of the behavior and structure of a description of the realization of frequency meter 8, 4 0 detection circuit principle of the amendment note
Platform: | Size: 14336 | Author: 黎明 | Hits:

[VHDL-FPGA-Verilog] 745221frequency

Description: 用Verilog HDL / VHDL实现的数字频率计（完整实验报告）-Using Verilog HDL/VHDL realization of digital frequency meter (complete test report)
Platform: | Size: 145408 | Author: 倪亮 | Hits:

[VHDL-FPGA-Verilog] fre500000

Description: 等精度数字频率计的Verilog源码，从上到下的设计思路，分为6个模块。上过Altera公司的FPGA板。 供大家参考，希望大家不要照抄！-Such as precision digital frequency meter Verilog source code, from top to bottom of design ideas, divided into six modules. Been to Altera' s FPGA boards. For your reference, hope you will not copy!
Platform: | Size: 2956288 | Author: 程永生 | Hits:

[VHDL-FPGA-Verilog] digital-frequency

Description: 数字频率计 采用Verilog语言编写，分为8个模块，分别是计数器，门控，分频，寄存器，多路选择，动态位选择，BCD译码模块-Digital frequency meter using Verilog language, divided into eight modules, namely, the counter, gated, frequency, register, multiplexer, Dynamic Choice, BCD decoding module
Platform: | Size: 1265664 | Author: multidecoder | Hits:

[VHDL-FPGA-Verilog] verilog

Description: verilog实现的数字频率计8位数码管输出显示同时矩形波分档输出-verilog implementation of digital frequency meter
Platform: | Size: 10240 | Author: 龚俊杰 | Hits:

[VHDL-FPGA-Verilog] Digital_frequency_meter

Description: 本项目基于等精度测量频率的原理,利用Verilog硬件描述语言设计实现了频率计内部功能模块,对传统的等精度测量方法进行了改进,增加了测量脉冲宽度的功能 采用STC89C52单片机进行数据运算处理,利用液晶显示器对测量的频率、占空比进行实时显示。充分发挥FPGA(现场可编程门阵列)的高速数据采集能力和单片机的高效计算与控制能力,使两者有机地结合起来。-The project is based on the principle of equal precision frequency measurement, using Verilog hardware description language design and implementation of the frequency meter internal function modules, such as the traditional measurement accuracy was improved by increasing the pulse width measurement function use STC89C52 MCU data processing operations the use of liquid crystal display on the measurement of the frequency, duty cycle displayed in real time. Full FPGA (field programmable gate array), high-speed data acquisition capabilities and high-performance computing and microcomputer control to organically combine the two.
Platform: | Size: 1339392 | Author: swekey | Hits:

[VHDL-FPGA-Verilog] frequency-meter

Description: 基于Verilog HDL语言，编写的频率计。-Based on Verilog HDL language, written in frequency meter.
Platform: | Size: 306176 | Author: xxy | Hits:

[VHDL-FPGA-Verilog] frequency

Description: 基于Verilog HDL数字频率计的设计与实现(Design of Verilog HDL Digital Frequency Meter)
Platform: | Size: 4366336 | Author: Tony_C | Hits:

[VHDL-FPGA-Verilog] frequency

Description: 用于FPGA开发，使用VERILOG语言编写，并在QUARTUS II仿真平台仿真，实现频率计的功能。(It is used in FPGA development, written in VERILOG language, and simulated on the QUARTUS II simulation platform to realize the function of the frequency meter.)
Platform: | Size: 371712 | Author: 丶静俟 | Hits:

[Documents] Verilog-数字频率计

Description: 实现了利用verilog在FPGA系统上实现的数字频率计，三个档位可供选择。(The digital frequency meter implemented on the FPGA system by Verilog is realized, and three files can be selected.)
Platform: | Size: 1902592 | Author: 娃娃哦哦 | Hits:
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