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[Other resource] FFT-FPGA

Description: 16位定点FFT-DSP的FPGA实现，相关代码和实用说明
Platform: | Size: 3834691 | Author: 杨合 | Hits:

[Other Embeded program] 16路复接器的FPGA代码

Description: 该复接器把16路并行信号转为一路串行信号
Platform: | Size: 1811 | Author: tomclus006@163.com | Hits:

[Other] FFT16

Description: 基于FPGA的16点FFT快速傅立叶变换的Verilog源代码。-the FFT implement of Verilog based on FPGA
Platform: | Size: 2048 | Author: lsd | Hits:

[Communication] 曼彻斯特码

Description: 今天看了一下从fpga上下的曼彻斯特编解码的程序，感觉不是很清楚，仿真了一下，更迷茫了，大家看看为啥这程序要这么编呢？ 程序比较长，不过写的应该还是不错的，看了后应该有收获。 总的思路是这样： 1 通过一个高频的时钟检测wrn信号，如果检测到上升沿，则表明开始编码，将输入的8位数据转为串行，并编码，然后输出。 2 定时信号是从高频时钟16分频后得到的，在wrn上升沿后16分频使能，在编码结束后禁止分频输出。 3 no_bits_sent记录串行输出的位数，应该是从0010到1001输出串行信号，到1010时编码结束，输出tbre表明编码完成。 问题是no_bits_sent在到了1010后还是会继续增加，直到1111，然后clk1x_enable 就为0，无法分频，clk1x就为一直流信号。这样当clk1x_enable再次为1的时候，no_bits_sent也不会增加，在1111上不变，clk1x_enable又会回到0了。 -today they simply watched from across the Manchester encoding and decoding process, not feeling very well, simulation a bit more confused, we look at procedures to be ready this series so? Procedures longer, but should still write good, it should have read harvest. The thinking is this : one by a high-frequency clock signal detection international, if detected rising edge, it indicates the beginning of coding will be entered into the eight to serial data and coding, and then output. Two timing signals from the high-frequency clock frequency 16 hours after the the international rising edge after 16 minutes frequency to enable the coding after the end of Prohibition-frequency output. 3 no_bits_sent record median serial output, it should be from 0010 to 1001 serial output signal to the end of
Platform: | Size: 5120 | Author: 游畅 | Hits:

[source in ebook] 16fft_vhdl.ZIP

Description: 一个用FPGA实现的16FFT,仅供参考不作为工程文件-with an FPGA 16FFT, not only as a reference document projects
Platform: | Size: 266240 | Author: 武第 | Hits:

[VHDL-FPGA-Verilog] cpuTerminate

Description: 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
Platform: | Size: 2108416 | Author: 宋文强 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[Other] PCI_Bridge_Guest_UART

Description: 这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序，用verilog实现，ise7.1，不知道这里可不可以上传硬件的程序~-pci-wishbone nuclear and nuclear Serial 16,450 in the TP xilinx They achieved a serial program, verilog realization ise7.1. Can here do not know the procedures upload hardware ~
Platform: | Size: 8427520 | Author: heartbeat | Hits:

[Other] caideng

Description: 用VHDL语言描述十六路彩灯的设计其开发均在FPGA中-using VHDL description of 16 Lantern Road, the design of its development is in FPGA
Platform: | Size: 142336 | Author: 侯同 | Hits:

[VHDL-FPGA-Verilog] fft

Description: 16卫浮点FFT算法的VHDL实现，有测试文件。-16 floating-point FFT algorithm Wei VHDL realize, have the test paper.
Platform: | Size: 418816 | Author: | Hits:

[3G develop] mit-ofdm-wifi

Description: MIT关于OFDM收发器、WIFI收发器的ASIC和 FPGA硬件开发源码及资料，比较不错的资料OFDM: OFDM transceiver (transmitter and receiver), highly parameterized to cover 802.11a (WiFi), 802.16 (WiMax) and others in the future. Support for 802.15 (WUSB) is currently being worked on. 802.11a: 802.11a WiFi transmitter-MIT on the OFDM transceiver, WIFI transceiver ASIC and FPGA hardware development source code and information, good information comparing OFDM: OFDM transceiver (transmitter and receiver), highly parameterized to cover 802.11a (WiFi), 802.16 (WiMax) and others in the future. Support for 802.15 (WUSB) is currently being worked on.802.11a: 802.11a WiFi transmitter
Platform: | Size: 802816 | Author: test | Hits:

[Software Engineering] LED

Description: 本文介绍了一种全新的LED显示屏控制解决方案，主要使用Altera cyclone飓风FPGA和16位凌阳单片机SPCE061A作为主控器件，采用较普遍的74LS595作为LED 显示屏显示驱动芯片。-In this paper, a new LED display control solution, the main use of Altera cyclone hurricane FPGA and 16-bit single-chip Sunplus SPCE061A as a master device, using the more common 74LS595 as an LED screen display driver chip.
Platform: | Size: 370688 | Author: 上官婉儿 | Hits:

[VHDL-FPGA-Verilog] FFT-FPGA

Description: 16位定点FFT-DSP的FPGA实现，相关代码和实用说明-16-bit fixed-point FFT-DSP realize the FPGA, the relevant code and practical description
Platform: | Size: 3834880 | Author: 杨合 | Hits:

[VHDL-FPGA-Verilog] 1602_jp

Description: FPGA lcd显示程序，可以扫描键盘输入，并在lcd上显示，-FPGA lcd display program, you can scan the keyboard input and display in lcd,
Platform: | Size: 478208 | Author: zdy | Hits:

[VHDL-FPGA-Verilog] fpga-mcu

Description: 利用uart接口，51单片机和FPGA完成16位宽的数据通信，包括数据的幷串转换等。-Uart interface 51 of microcontroller and FPGA 16-bit wide data communications, and including Bing string of data conversion.
Platform: | Size: 628736 | Author: 张朗 | Hits:

[Other] 《阿东 手把手教你学FPGA》完美公开版 (1)

Description: 本书主要讲解 FPGA 的程序设计,以一款热销的 FPGA 开发板为例,介绍学习 FPGA 和 Ver-ilog ,以及 FPGA 开发板的硬件配置,重点是第 3 章的 16 个典型实例程序,由简单到复杂,最后是FPGA 的设计心得。 本书适合电子、通信、自动化等相关专业的本科生以及从事 FPGA 开发/ IC 设计/ PCB 等相关 职业的初学者阅读参考。(The program design of the main book on the FPGA, with a hot FPGA development board as an example, introduces the study of FPGA and Ver-ilog, and FPGA development board hardware configuration, the focus is on 16 typical examples of procedures of the third chapter, from simple to complex, finally the design experiences of FPGA.)
Platform: | Size: 23864320 | Author: 红蓝狐 | Hits:

[VHDL-FPGA-Verilog] 彩色图片转换16进制数据用此代码

Description: 彩色图片转换 16进制数据用此代码---基于fpga的图像处理(Using this code to convert 16 - band data in a color picture)
Platform: | Size: 86016 | Author: 布列塔尼 | Hits:

[Communication-Mobile] 16-QAM调制系统的FPGA实现

Description: 16-QAM调制系统的FPGA实现 正交幅度调制(QAM)由于具有很高的频谱利用率被DVB-C等标准选做主要的调制技术。与多进制PSK(MPSK)调制不 同，OAM调制采取幅度与相位相结合的方式，因而可以更充分地利用信号平面，从而在具有高频谱利用效率的同时可以获得比MPSK更低的误码率。(FPGA implementation of 16-QAM modulation system)
Platform: | Size: 1392640 | Author: JF1234 | Hits:

[VHDL-FPGA-Verilog] 基于FPGA的多路同步脉冲发生器设计1

Description: 采用FPGA（现场可编程门序列）编写VHDL语言设计多路同步脉冲发生器，对信号进行分频处理，实现四路信号相位相差T/16和T/8的延迟相位输出，实现的四路脉冲与传统的脉冲同步器不同，它具有高集成度，高通用性，容易调整和高可靠性等特点。(Using FPGA (field programmable gate sequence) to write VHDL language to design multi-channel synchronous pulse generator, to divide the frequency of the signal, to achieve the four-way signal phase difference T / 16 and T / 8 delay phase output, the realization of the four-way pulse is different from the traditional pulse synchronizer, it has the characteristics of high integration, high-throughput, easy adjustment and high reliability.)
Platform: | Size: 10240 | Author: 哈哈哈哈daxiao | Hits:
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