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[VHDL-FPGA-Verilog] Verilog_chinesegolden

Description: Verilog_黄金参考中文版经典 EDA编程人员进入编程工作首要的学习资料-Verilog_ reference to the Chinese version of the classic gold EDA programmers to enter the programming first and foremost learning materials
Platform: | Size: 468992 | Author: 陈斌 | Hits:

[VHDL-FPGA-Verilog] ADcaiyang

Description: A/D采样控制模块设计 A/D采样控制模块负责控制外部ADC0809芯片多路模拟输入量的选通以及实现对A/D采样过程的合理控制。此部分的设计根据《EDA技术与VHDL》P211——P212的例8-2编写，所不同的是这里将书中“ADDA<=1”的赋值语句改为“ADDA <=EN”，EN是所设置的输入按键用来控制INO与IN1间的通道选择。 -A/D sampling control module designed A/D sampling control modules responsible for controlling external ADC0809 chip multi-channel analog input, as well as the amount of strobe to achieve A/D sampling the reasonable control of the process. This part of the design under the EDA technology and VHDL P211- P212 preparation of the cases of 8-2, the difference is that here the book ADDA <= 1 of the assignment changed to ADDA <= EN , EN is the set of input buttons used to control between INO and IN1 channel selection.
Platform: | Size: 1024 | Author: xuye | Hits:

[SCM] SMC1602A

Description: SMC1602A液晶显示器子程序,SMC1602A液晶显示器子程序 [日期：2008-01-20] 来源：EDA网作者：郭森 [字体：大中小] LCD SMC1602A显示模块-SMC1602A liquid crystal display subroutine, SMC1602A liquid crystal display subroutine [date :2008-01-20] Source: EDA network Author: Sam [Font: Xinhuanet] LCD SMC1602A display module
Platform: | Size: 1024 | Author: 郭森 | Hits:

[Software Engineering] 2006EDA

Description: 2006全国大学生电子竞赛EDA课程设计题目-2006 National Undergraduate Electronic Design Contest EDA Course Title
Platform: | Size: 413696 | Author: betazhang | Hits:

[VHDL-FPGA-Verilog] HardwareflowerdesignEDAdesignreport

Description: 硬件电子琴电路设计EDA设计报告,开发环境VHDL-Hardware electric circuit design EDA design report, VHDL development environment
Platform: | Size: 48128 | Author: 百事可乐 | Hits:

[Other] EDA

Description: EDA的一些小实例，挺有用，可以参考一下-EDA of some small examples, quite used, you can refer to
Platform: | Size: 22260736 | Author: ghm | Hits:

[Other] Modelling_Analysis_Synthesis_Asynchronous_Control_

Description: EDA 软件算法；采用Petri－net对异步控制电路进行综合，得到硬件可实现电路。-EDA software algorithms using Petri-net for asynchronous control circuit synthesis, the hardware circuit can be realized.
Platform: | Size: 262144 | Author: leo z | Hits:

[VHDL-FPGA-Verilog] eda

Description: 用VHDL编写的一个出租车计费器，起步6元计2公里，此后每半公里计0.8元，停车等待每2.5分计0.8元。通过仿真，但未下载到CPLD测试-Using VHDL prepared a taxi meter, starting 6 dollars two kilometers, and thereafter every half a kilometer of 0.8 yuan, parking to wait for every 2.5 hours of 0.8 yuan. Through simulation, but not downloaded to the CPLD test
Platform: | Size: 164864 | Author: 左大 | Hits:

[VHDL-FPGA-Verilog] infrared_receive

Description: 接收解码用VHDL语言编写程序，在EDA实验板上实现解码，要求具有以下功能：（a）将一体化红外接收解调器的输出信号解码（12个单击键、6个连续键，单击键编号为7－18，连续键编码为1－6），在EDA实验板上用七段数码管显示出来；（b）当按下遥控器1—6号连续键时，在EDA实验板上用发光二极管点亮作为连续键按下的指示，要求遥控器上连续键接下时指示灯点亮，直到松开按键时才熄灭，用于区别单击键。（c）EDA实验板上设置四个按键，其功能等同于遥控器上的1—4号按键，当按下此四个按键时七段数码管分别对应显示“1”、“2”、“3”、“4”。（d）每当接收到有效按键时，蜂鸣器会发出提示音。
Platform: | Size: 145408 | Author: 钟允 | Hits:

[VHDL-FPGA-Verilog] eda

Description: 用VHDL编的两位BCD加法器用VHDL编的两位BCD加法器-Using VHDL made two BCD adder VHDL transparencies made two BCD adder
Platform: | Size: 1024 | Author: 王海峰 | Hits:

[Graph program] count

Description: EDA实验--利用宏功能模块实现的计数器: 利用-MegaWizard Plug-In Manager创建一个16位计数器，具备正逆计数以及预置，清0功能。本实验由RESET健清0，PSW1健控制预制数，按下置入1234，PSW2控制正逆计数，按下递减计数，弹起正向计数。利用VGA作为输出设备，显示计数值，编辑源程序，观察实验结果。-EDA experiments using macro function modules realize the counter: use-MegaWizard Plug-In Manager to create a 16-bit counter, with counting and the inverse is preset, the Qing 0 function. The experiment was conducted by RESET Kin-ching 0, PSW1 prefabricated Kin control number, pressed into 1234, PSW2 control is against the count, press the reduced count, count up positive. The use of VGA as output device, shows the value, edit the source code to observe the experiment results.
Platform: | Size: 2048 | Author: 黄龙 | Hits:

[Embeded-SCM Develop] testram_1

Description: EDA实验--RAM实验:利用-MegaWizard Plug-In Manager创建一个16×8的RAM，通过编程对RAM进行读写并在显示器上显示。本例使用三个按键PSW3，PSW2，PSW1，分别对应顶层文件中的x，y，we，we＝1对RAM写，xy＝11时，写入10101011；当xy＝01时，写入01010101；当xy＝10时，写入10101010。we＝0时，对RAM读出。三个按键按下时为0，当PSW1健按下时对RAM进行读出。 -EDA Experimental RAM experiment: the use-MegaWizard Plug-In Manager to create a 16 × 8 of the RAM, through the programming of the RAM read and write and displayed on the monitor. This example uses three buttons PSW3, PSW2, PSW1, corresponding to top-level document x, y, we, we = 1 on RAM write, xy = 11, the write 10101011 when xy = 01 hours, write 01010101 when xy = 10, the write 10101010. we = 0 when read out of RAM. Press the three keys for 0, when PSW1 Kin-pressed to read out of RAM.
Platform: | Size: 4096 | Author: 黄龙 | Hits:

[VHDL-FPGA-Verilog] transfer_1

Description: EDA实验--UART串口实验：UART 主要有由数据总线接口、控制逻辑、波特率发生器、发送部分和接收部分等组成。UART 发送器 --- 发送器每隔16 个CLK16 时钟周期输出1 位，次序遵循1位起始位、8位数据位（假定数据位为8位）、1位校验位（可选）、1位停止位。 UART 接收器 --- 串行数据帧和接收时钟是异步的，发送来的数据由逻辑1 变为逻辑0 可以视为一个数据帧的开始。接收器先要捕捉起始位，确定rxd 输入由1 到0，逻辑0 要8 个CLK16 时钟周期，才是正常的起始位，然后在每隔16 个CLK16 时钟周期采样接收数据，移位输入接收移位寄存器rsr，最后输出数据dout。还要输出一个数据接收标志信号标志数据接收完。波特率发生器 --- UART 的接收和发送是按照相同的波特率进行收发的。波特率发生器产生的时钟频率不是波特率时钟频率，而是波特率时钟频率的16 倍，目的是为在接收时进行精确地采样，以提出异步的串行数据。 --- 根据给定的晶振时钟和要求的波特率算出波特率分频数。
Platform: | Size: 2048 | Author: 黄龙 | Hits:

[VHDL-FPGA-Verilog] eda-vhdl-traficlightctrl

Description: 用VHDL语言描述和实现的一个交通灯控制器，该交通灯系统为一个十字路口交通管理信号灯，用于主干道与乡间公路的交叉路口，要求是优先保证主干道的畅通，因此平时处于“主干道绿灯，乡间道红灯”状态，只有在乡间公路有车辆要穿行主干道时才将交通灯切向“主干道红灯，乡间道绿灯”，一旦乡间公路无车辆通过路口，交通灯又回到“主绿，乡红”的状态。此外，主干道每次通行的时间不得短于1分钟，乡间公路每次通行时间不得长于20秒。而在两个状态交换过程中出现的“主黄，乡红”和“主红，乡黄”状态，持续时间都为4秒。
Platform: | Size: 1024 | Author: 黄然 | Hits:

[Other] clock

Description: 本文介绍一种利用 EDA技术和VHDL 语言 ,在MAX+PLUSⅡ环境下,设计了一种新型的智能密码锁。它体积小、功耗低、价格便宜、安全可靠,维护和升级都十分方便,具有较好的应用前景-This paper presents a use of EDA technologies and VHDL language, in MAX+ PLUS Ⅱ environment, design a new type of intelligent locks. Its small size, low power consumption, cheap, safe, reliable, maintenance and upgrade are very convenient, has good application prospects
Platform: | Size: 67584 | Author: 叶仔 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 实用VHDL教程,书中内容包括:了解数字集成电路的结构特点掌握常用EDA工具的基本使用方法掌握VHDL的基本语法和主要编程要点掌握常用数字单元电路的VHDL设计了解数字集成系统的基本设计方法-VHDL Tutorial practical book include: understanding the structural characteristics of digital integrated circuits commonly used EDA tools to master the basic use of VHDL to master basic grammar and the main programming elements commonly used to master the digital unit of VHDL circuit design of digital integrated system to understand the basic design method
Platform: | Size: 3379200 | Author: ff | Hits:

[Other] EDA

Description: EDA技术介绍，关于EDA的简要介绍-EDA technology introduction, a brief introduction on the EDA
Platform: | Size: 350208 | Author: 尹福斌 | Hits:

[VHDL-FPGA-Verilog] EDA_17392

Description: EDA得源码程序，绝对认证。适合EDA实验箱，仿真实验等基础实验-A source EDA procedures, absolute certification. EDA suitable experimental boxes, and so on the basis of simulation experiment
Platform: | Size: 1784832 | Author: 杨之皓 | Hits:

[Embeded-SCM Develop] DDS

Description: 基于DD的数字移相正弦信号发生器设计 EDA技术在全国大学生设计竞赛中的应用-err
Platform: | Size: 238592 | Author: Alex | Hits:

[Other Embeded program] DDS

Description: 基于DDS的数字移相正弦信号发生器设计，EDA技术在全国大学生电子设计竞赛中的应用-DDS-based digital phase-shifting sinusoidal signal generator design, EDA Technology in the National Undergraduate Electronic Design Contest Application
Platform: | Size: 222208 | Author: Alex | Hits:

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[VHDL-FPGA-Verilog] Verilog_chinesegolden

[VHDL-FPGA-Verilog] ADcaiyang

[SCM] SMC1602A

[Software Engineering] 2006EDA

[VHDL-FPGA-Verilog] HardwareflowerdesignEDAdesignreport

[Other] EDA

[Other] Modelling_Analysis_Synthesis_Asynchronous_Control_

[VHDL-FPGA-Verilog] eda

[VHDL-FPGA-Verilog] infrared_receive

[VHDL-FPGA-Verilog] eda

[Graph program] count

[Embeded-SCM Develop] testram_1

[VHDL-FPGA-Verilog] transfer_1

[VHDL-FPGA-Verilog] eda-vhdl-traficlightctrl

[Other] clock

[VHDL-FPGA-Verilog] VHDL

[Other] EDA

[VHDL-FPGA-Verilog] EDA_17392

[Embeded-SCM Develop] DDS

[Other Embeded program] DDS

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