Description: 数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms Platform: |
Size: 808948 |
Author:萧飒 |
Hits:
Description: 数字计时器，使用VHDL语言编写，使用数码管显示，精确到ms-digital timer, the use of VHDL development, the use of digital control, the precision of the ms Platform: |
Size: 808960 |
Author:萧飒 |
Hits:
Description: 1.高精度数字秒表（0.01秒的vhdl语言实现）
2.具有定时，暂停，按键随机存储，翻页回放功能；
3.对30M时钟分频产生显示扫描时钟
4.精度高达0.01s,并且可以通过改变主频来更改分频比和记数间隔，可控性高。
5.模块化设计，其中的许多函数可以成为vhdl语言的通用经典例子（包含分频电路设计，动态扫描时钟设计，译码电路设计，存储器设计，存储回放显示设计）-1. High-precision digital stopwatch (0.01 seconds vhdl language) 2. With a timer, suspended Random memory keys, flip playback function; 3. right 30M clock frequency scan have revealed four clock. Precision high 0.01s and and can be changed to alter the frequency than the frequency interval and Hutchison, controlled high. 5. Modular design, Many of these functions can become the common language vhdl classic examples (including sub-frequency circuit design, Dynamic scanning clock design, decoding circuit design, memory design, storage intervals showed Design) Platform: |
Size: 2048 |
Author:方周 |
Hits:
Description: 描述了24小时计时的数字钟，同时具有分秒计时的功能-Described a 24-hour digital time clock, at the same time every minute timer function Platform: |
Size: 11264 |
Author:金珊珊 |
Hits:
Description: VHDL语言设计的数字钟 具有时分秒三段显示-VHDL language designed with time-accurate digital clock shows three paragraphs Platform: |
Size: 1024 |
Author:孙明 |
Hits:
Description: 这时一个关于数字钟的VHDL程序，有计时、校时、报时等功能-When a digital clock on the VHDL program, there is time, school time, timer and other functions Platform: |
Size: 80896 |
Author:吴凯 |
Hits:
Description: 基于VHDL语言，实现时钟功能，显示时间从00：00：00到23：59：59，并将其输出信号转换为数码管信号-Based on the VHDL language, to achieve the clock function, display time from 00:00:00 to 23:59:59, and the output signal is converted to digital control signals Platform: |
Size: 498688 |
Author:陈伟 |
Hits:
Description: 这是一个基于FPGA设计的24时多功能数字钟，具有正常星期、时、分、秒计时，动态显示，保持、清零、快速校分、整点报时、闹钟功能。-This is an FPGA-based design of multi-function digital clock 24 hours, with a normal week, hours, minutes, seconds, timing, dynamic display, maintaining, resetting, fast school hours, the whole point timekeeping, alarm clock function. Platform: |
Size: 791552 |
Author:紫郢寒光 |
Hits:
Description: 基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency module, " the minutes and seconds" counter module, data selection module, timer module, dynamic scanning display and decoding module. Get a will " ," and " division" and " seconds" display on the human visual organ of the timing device. It' s time for the 24-hour period, indicating full scale as 23:59:59, and another school, the school hours and the whole hour, and through digital tube display driver circuit timing results. Platform: |
Size: 63488 |
Author:sunnan |
Hits:
Description: 用VHDL语言编写的数字钟程序，可以实现计时功能，且具有整点报时功能，能够实现时、分、秒的十进制显示。-With VHDL language，it can realize the function of digital clock timer. Platform: |
Size: 3072 |
Author:yanzi |
Hits:
Description: 使用VHDL语言设计数字钟。
数字钟由晶振、分频器、计时器、译码器、显示器等组成-Digital clock design using the VHDL language. Digital clock from the crystal oscillator, frequency divider, timer, decoder, display and other components Platform: |
Size: 482304 |
Author:zhangsheng |
Hits:
Description: 用VHDL实现多功能数字钟 闹铃 计时 动显 报时等-VHDL realization of multi-functional digital clock with alarm timer was timekeeping and other fixed Platform: |
Size: 445440 |
Author:顾利琳 |
Hits:
Description: 本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自
顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测
试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐
闹铃。-The design uses the silicon chip EP1C12Q240C8 produced by the company of
ALTERA. And with the help of VHDL, the design of a digital clock is completed
using the top-down approach under Quartus Ⅱ, finally carried out in the SmartSOPC.
Functions of the digital clock are: timer, showing day, setting time, resetting, Chime
on every hour, and alarm with music. Platform: |
Size: 231424 |
Author:费孝海 |
Hits:
Description: 设计一个多功能数字钟，要求显示格式为小时－分钟－秒钟，整点报时，报时时间为10 秒，即从整点前10 秒钟开始进行报时提示，喇叭开始发声，直到过整点时，在整点前5 秒LED 开始闪烁，过整点后，停止闪烁。系统时钟选择时钟模块的10KHz，要得到1Hz 时钟信号，必须对系统时钟进行10,000次分频。调整时间的的按键用按键模块的S1 和S2，S1 调节小时，每按下一次，小时增加一个小时，S2 调整分钟，每按下一次，分钟增加一分钟。另外用S8 按键作为系统时钟复位，复位后全部显示00－00－00。-The design of a multi-function digital clock, required to display format for hours: Minutes: seconds, the whole point timekeeping and timer for 10 seconds, namely the whole point of 10 seconds before start timekeeping prompt, horn began to sound, until the whole point, in the whole point of 5 seconds the LED flashes, over the whole point, stop flicker. System clock to the clock module 10KHz, to get the 1Hz clock signal, the system must be 10000 times the system clock. Adjust the time of the keys with the key module S1 and S2, S1 adjust the hours, each press once, an hour to increase an hour, S2 to adjust the minutes, every time you press a minute, a minute. We also use the S8 button as the system clock reset, reset all display 00-00-00. Platform: |
Size: 7658496 |
Author:冯雨娴 |
Hits:
Description: 用VHDL 语言设计数字钟，实现在数码管上显示分钟和秒，并且可以手动调节分钟，
实现分钟的增或者减。该设计包括以下几个部分：
（1）分频电路的设计，产生1Hz 的时钟信号，作为秒计时脉冲；
（2）手动调节电路，包括“时增”“时减”“分增”“分减”。
（3）时分秒计时电路。
（4）7 段数码管显示电路。
将 SW1 和SW2 初始状态均置为高电平。拨动开关SW1 到低，分钟进行加计数，秒停
止计数，当计数到59 时，从00 开始重新加计数，将SW1 拨动到高时，在当前状态进行计时。当拨动开关SW2 为低时，分钟进行减计数，秒停止计数，当减到0 时，从59 开始减计数，将SW2 拨动到高时，在当前状态进行计时。-VHDL language with the design of digital clock, in the digital display minutes and seconds, and can manually adjust the minutes,
To achieve the increase or decrease minutes. The design includes the following sections:
(1) frequency circuit design, resulting in 1Hz clock signal, as the second time pulse
(2) manual adjustment of the circuit, including when the increase when the minus points by sub-minus.
(3) when the minutes and seconds timer circuit.
(4) 7-segment LED display circuit.
Set the initial state of SW1 and SW2 to high level. Toggle switch SW1 to low, minute to count up, seconds to stop
Stop counting, when counting to 59, 00 to re-count the start, will SW1 toggle to high, in the current state of time. When the switch SW2 is low, the timer counts down in minutes and stops counting in seconds. When it decreases to 0, it counts down 59, and turns SW2 to HIGH to count in the current state. Platform: |
Size: 495616 |
Author:panda |
Hits:
Search - digital clock timer vhdl