Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: clock Download
 Description: VHDL realization of multi-functional digital clock with alarm timer was timekeeping and other fixed
 Downloaders recently: [More information of uploader gll52016]
 To Search:
File list (Check if you may need any files):
clock\1.bdf
.....\alarm.bsf
.....\alarm.vhd
.....\alarm.vhd.bak
.....\db\main.analyze_file.qmsg
.....\..\main.asm.qmsg
.....\..\main.cbx.xml
.....\..\main.cmp.bpm
.....\..\main.cmp.cdb
.....\..\main.cmp.ecobp
.....\..\main.cmp.hdb
.....\..\main.cmp.logdb
.....\..\main.cmp.rdb
.....\..\main.cmp_bb.cdb
.....\..\main.cmp_bb.hdb
.....\..\main.cmp_bb.logdb
.....\..\main.cmp_bb.rcf
.....\..\main.dbp
.....\..\main.db_info
.....\..\main.eco.cdb
.....\..\main.eds_overflow
.....\..\main.fit.qmsg
.....\..\main.fnsim.cdb
.....\..\main.fnsim.hdb
.....\..\main.fnsim.qmsg
.....\..\main.hier_info
.....\..\main.hif
.....\..\main.map.bpm
.....\..\main.map.cdb
.....\..\main.map.ecobp
.....\..\main.map.hdb
.....\..\main.map.logdb
.....\..\main.map.qmsg
.....\..\main.map_bb.cdb
.....\..\main.map_bb.hdb
.....\..\main.map_bb.logdb
.....\..\main.pre_map.cdb
.....\..\main.pre_map.hdb
.....\..\main.psp
.....\..\main.pss
.....\..\main.rtlv.hdb
.....\..\main.rtlv_sg.cdb
.....\..\main.rtlv_sg_swap.cdb
.....\..\main.sgdiff.cdb
.....\..\main.sgdiff.hdb
.....\..\main.signalprobe.cdb
.....\..\main.sim.cvwf
.....\..\main.sim.hdb
.....\..\main.sim.qmsg
.....\..\main.sim.rdb
.....\..\main.sim_ori.vwf
.....\..\main.sld_design_entry.sci
.....\..\main.sld_design_entry_dsc.sci
.....\..\main.sta.qmsg
.....\..\main.sta.rdb
.....\..\main.syn_hier_info
.....\..\main.tiscmp0.ddb
.....\..\main.tiscmp2.ddb
.....\..\prev_cmp_main.asm.qmsg
.....\..\prev_cmp_main.fit.qmsg
.....\..\prev_cmp_main.map.qmsg
.....\..\prev_cmp_main.sim.qmsg
.....\..\prev_cmp_main.sta.qmsg
.....\..\wed.wsf
.....\fen.bsf
.....\fen.vhd
.....\fen.vhd.bak
.....\fen.vwf
.....\fenpin.bsf
.....\fenpin.vhd
.....\fenpin.vhd.bak
.....\jishu.bdf
.....\jishu.bsf
.....\jishu.vwf
.....\led.bsf
.....\led.vhd
.....\led.vhd.bak
.....\main.asm.rpt
.....\main.cdf
.....\main.done
.....\main.dpf
.....\main.fit.rpt
.....\main.fit.smsg
.....\main.fit.summary
.....\main.flow.rpt
.....\main.map.rpt
.....\main.map.summary
.....\main.pin
.....\main.pof
.....\main.qpf
.....\main.qsf
.....\main.qws
.....\main.sim.rpt
.....\main.sof
.....\main.sta.rpt
.....\main.sta.summary
.....\miao.bsf
.....\miao.vhd
.....\miao.vhd.bak
.....\miao.vwf
    

CodeBus www.codebus.net