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[VHDL-FPGA-Verilog] ref-sdr-sdram-vhdl

Description: DDR控制器的VHDL源代码.采用FPGA实现DDR接口控制器,适用于Altera的FPGA,最高频率可到100M-DDR controller VHDL source code. Using FPGA DDR interface controller, applicable to Altera FPGA, the highest frequency available 100M
Platform: | Size: 776192 | Author: 张涛 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram控制器 这里考虑将SDRAM控制器结合目前项目开展来做相应的模块，而不做SDRAM通用控制器，这样也是考虑了FPGA的器件资源而采取的措施。同时编写的逻辑简单，没有多余的逻辑资源有利于提高控制器的速度，满足最后的设计要求。-SDRAM controller here consider SDRAM controller current projects do the corresponding module, but not so common SDRAM controller, as well as consider the FPGA device resources and the measures taken. While the preparation of simple logic, the logic is no spare resources to improve the speed controller to meet the final design requirements.
Platform: | Size: 3072 | Author: 林博 | Hits:

[File Format] DDR_SDRAM_use_in_embedded

Description: 很多嵌入式系统，特别是应用于图像处理与高速数据采集等场合的嵌入式系统，都需要高速缓存大量的数据。DDR（Double Data Rate，双数据速率）SDRAM由于其速度快、容量大，而且价格便宜，因此能够很好地满足上述场合对大量数据缓存的需求。但DDR SDRAM的接口不能直接与现今的微处理器和DSP的存储器接口相连，需要在其间插入控制器实现微处理器或DSP对存储器的控制。-many embedded systems, especially for image processing and high-speed data acquisition, and so on the embedded system, Cache require large amounts of data. DDR (Double Data Rate, double-data rate) SDRAM due to its speed, large capacity, and their prices are cheaper, it can be a very good occasion to meet these massive data cache demand. But DDR SDRAM interface directly with today's microprocessor and DSP memory interface connected, During the need to insert controller microprocessor or DSP memory of the control.
Platform: | Size: 237568 | Author: joucan | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR sdram 包含的完整的源码,仿真的相关文件-DDR sdram contains complete source code, simulation of the relevant documents
Platform: | Size: 1021952 | Author: 飞翔 | Hits:

[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr

Description: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Platform: | Size: 114688 | Author: | Hits:

[VHDL-FPGA-Verilog] ddr_ctrl

Description: verilog hdl coding DDR sdram control for fpga -verilog hdl coding DDR sdram control for fpga
Platform: | Size: 27648 | Author: 王郁 | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: 基于FPGA 实现DDR SDRAM的控制器-FPGA-based realization of DDR SDRAM controller
Platform: | Size: 474112 | Author: 张宁 | Hits:

[VHDL-FPGA-Verilog] t26a_ibis

Description: ddr sdram 的控制代码，采用VHDL语言书写-ddr sdram control code, the use of VHDL language
Platform: | Size: 281600 | Author: zxb | Hits:

[SCM] DDR_SDRAM_DesignSummarize

Description: 基于Xilinx Spartan系列开发板的DDR SDRAM设计方案及经验总结!-Based on the Xilinx Spartan family of development boards and the DDR SDRAM design experience!
Platform: | Size: 338944 | Author: 曾娟丽 | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: ddr sdram 的vhdl实现，包括各个模块的实现以及仿真文件-ddr sdram realization of VHDL, including the realization of each module as well as the simulation file
Platform: | Size: 1021952 | Author: shroy | Hits:

[VHDL-FPGA-Verilog] DDR_SDRAM_controller

Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: | Size: 132096 | Author: xbl | Hits:

[Other] testbench

Description: ddr sdram controller datd module source code
Platform: | Size: 3072 | Author: KrishnaKishore | Hits:

[VHDL-FPGA-Verilog] DDRSDRAMControllerverilogcode

Description: 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。-This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.
Platform: | Size: 477184 | Author: fdasfds | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR SDRAM的资料，有兴趣的朋友可以下下来-DDR SDRAM information, interested to see friends down under
Platform: | Size: 73728 | Author: sy | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM

Description: DDR SDRAM的veilog hdl程序，经过验证 效果不错-DDR SDRAM' s veilog hdl procedures, good results verified
Platform: | Size: 475136 | Author: 寒心雪林 | Hits:

[Editor] DDRSDRAM

Description: DDR SDRAM设计及调试经验总结.pdf
Platform: | Size: 338944 | Author: arens09 | Hits:

[VHDL-FPGA-Verilog] sdram32

Description: DDR SDRAM source verilog source codes
Platform: | Size: 25600 | Author: sachin | Hits:

[VHDL-FPGA-Verilog] ddr_sdram_controller_vhdl

Description: DDR SDRAM控制器的VHDL代码已经测试-DDR SDRAM controller VHDL code
Platform: | Size: 13312 | Author: tom | Hits:

[VHDL-FPGA-Verilog] c_xapp851

Description: 这是xilinx应用指南xapp851的中文版本。本应用指南描述了在 Virtex™ -5 器件中实现的 200 MHz DDR SDRAM （JEDEC DDR400 (PC3200) 标准）控制器。本设计实现使用 IDELAY 单元调整读数据时序。读数据时序校准和调整在此控制器中完成。-This is the xilinx application note xapp851 the Chinese version. This application note describes the Virtex ™ -5 devices to achieve 200 MHz DDR SDRAM (JEDEC DDR400 (PC3200) standard) controller. The Design and Implementation of the use of IDELAY unit to adjust read data timing. Reading the data calibration and adjust the timing for completion of this controller.
Platform: | Size: 408576 | Author: 陈阳 | Hits:

[VHDL-FPGA-Verilog] ddr-sdram--chengxu

Description: ddr的控制程序，实用Verilog语言实现的非常的具体，非常无奈过的实用。-ddr
Platform: | Size: 14336 | Author: 张杰 | Hits:
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