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[VHDL-FPGA-Verilog] vhdl

Description: RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
Platform: | Size: 4096 | Author: 波波 | Hits:

[VHDL-FPGA-Verilog] freqdivfinal

Description: 用vhdl实现的分频器，可产生任意对主时钟的分频，从而是实现不同频率pwm的控制-Achieved using VHDL divider can produce any of the sub-master clock frequency, thereby achieving different frequency pwm control
Platform: | Size: 2048 | Author: | Hits:

[Windows Develop] clock-divider

Description: 这是一个关于时钟分频率器的程序，它可以实现频率的扩大。-This is a device on the clock frequency of the procedure, it can realize the expansion of the frequency.
Platform: | Size: 1024 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] clk-div

Description: VHDL code for a clock divider by 27 circuit with a resulting waveform with 50％ duty cycle..
Platform: | Size: 3072 | Author: 李军 | Hits:

[Communication-Mobile] E1_DCR

Description: 2MHz的数据时钟恢复电路，包括鉴相器、分频器及滤波器-2MHz data clock recovery circuit, including phase detector, divider and filter
Platform: | Size: 2048 | Author: Chen | Hits:

[VHDL-FPGA-Verilog] divider

Description: 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value of N is set up the corresponding figure
Platform: | Size: 1024 | Author: Tomy Lee | Hits:

[VHDL-FPGA-Verilog] FPQ

Description: 分频器的vhdl描述，在源代码中完成对时钟信号CLK的2分频,4分频,8分频,16分频-Divider vhdl description of the source code at the completion of the CLK clock signal frequency of 2 hours, 4 minutes frequency, frequency of 8 hours, 16 minutes frequency
Platform: | Size: 1024 | Author: LS | Hits:

[VHDL-FPGA-Verilog] FPGA_nCLK

Description: VHDL语言的高频时钟分频模块。一种新的分频器实现方法。-VHDL language at the high-frequency clock frequency modules. Divider to achieve a new method.
Platform: | Size: 49152 | Author: 李超 | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: This code contains the simple program that can be used for the clock divider to set any desireable clock from the master clock.
Platform: | Size: 1024 | Author: Shahzad | Hits:

[VHDL-FPGA-Verilog] signal_output

Description: 本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
Platform: | Size: 1160192 | Author: 蔡野锋 | Hits:

[VHDL-FPGA-Verilog] divider

Description: a clock divider vhdl code
Platform: | Size: 236544 | Author: mansih | Hits:

[VHDL-FPGA-Verilog] clock_divider

Description: clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc-clock divider for fpga in verilog and vhdl it contains counter.vhd clock1.v clock_divider.doc
Platform: | Size: 8192 | Author: sreejith | Hits:

[ELanguage] 20080108103305384

Description: 本系统是采用EDA技术设计的一个简易的八音符电子琴和音乐发生器，该系统基于计算机中时钟分频器的原理，采用自顶向下的设计方法来实现，它可以通过按键输入来控制音响。系统由乐曲自动演奏模块、乐器演示模块琴/乐功能选择模块、音调发生模块和数控分频模块五个部分组成。系统实现是用硬件描述语言VHDL按模块化方式进行设计，然后进行编程、时序仿真、整合。本系统功能比较齐全，有一定的使用价值.-The system is designed using EDA technology with a simple eight-note keyboard and music generator, the system clock divider based on the principle of the computer, using top-down design approach to achieve, it can control the audio through the key input to . The system automatically performed by the music module, instrument module piano demo/music feature selection module, tone modules, and numerical control frequency occurrence module of five parts. System implementation is to use hardware description language VHDL modular way by design, then programming, timing simulation, integration. The system functions and it has some value.
Platform: | Size: 50176 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] clock-divider

Description: VHDL code for clock divider circuit. There are two modules: one output divide by 4 and other outputs divide by 6
Platform: | Size: 1024 | Author: zpatel | Hits:

[VHDL-FPGA-Verilog] VHDL-counter

Description: 在数字电路中，常需要对较高频率的时钟进行分频操作，得到较低频率的时钟信号。我们知道，在硬件电路设计中时钟信号时非常重要的。 下面我们介绍分频器的VHDL描述，在源代码中完成对时钟信号CLK的2分频，4分频，8分频，16分频。 -In digital circuits, and often need high frequency clock divider operating in lower frequency clock signal. We know that when the clock signal in the hardware circuit design is very important. Here we introduce the VHDL description of the divider in the source code of the clock signal CLK divided by 2, 4 divider, divide by 8, divided by 16.
Platform: | Size: 86016 | Author: zhanghua | Hits:

[VHDL-FPGA-Verilog] clock-divider

Description: clock generator vhdl code
Platform: | Size: 1024 | Author: sgma | Hits:

[VHDL-FPGA-Verilog] VHDL-book3

Description: D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mod5cnt：模5计数器的设计 mod10Kcnt：时钟分频器的设计 morsea：任意波生成器的设计 sw2reg：加载开关量到寄存器的设计 shift_reg8：移位数据到移位寄存器的设计 scroll：滚动7段数码显示设计 fib：Fibonacci序列设计 pwm4：PWM控制直流电机设计 pwmg：PWM控制伺服电机位置设计-D_flipflop: 1-bit D flip-flop design D_fllipflop_behav: 4-bit D flip-flop design reg1bit: 1-bit register design reg4bit: 4-bit register design shiftreg4: general shift register design ring_shiftreg4: ring shift register design debounce4: elimination shake circuit design clock_pulse: clock pulse circuit design count3bit_gate: 3-bit counter design count3bit_behav: 3-bit counter design mod5cnt: Mode 5 counter design mod10Kcnt: clock divider design morsea: arbitrary waveform generator design sw2reg: Load switch to register the design shift_reg8: shift data into the shift register design scroll: Scroll 7-segment digital display design fib: Fibonacci Sequence Design pwm4: PWM controlled DC motor design pwmg: PWM servo motor position control design
Platform: | Size: 9017344 | Author: 贾诩 | Hits:

[Other] clock

Description: there's a clock divider for DE2 altra board clock (50MHz)
Platform: | Size: 623616 | Author: hosseinkhani | Hits:

[VHDL-FPGA-Verilog] rs485

Description: communication rs232 in vhdl with clock divider, counter, buffer, rs232tx, rs232rx.
Platform: | Size: 14336 | Author: le noach | Hits:

[Other] RPWM-matlab

Description: clock divider program by using VHDL
Platform: | Size: 869376 | Author: muthukumarvlsi | Hits:
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