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[VHDL-FPGA-VerilogFPGA_bit_clock_data_recovery

Description: 基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method
Platform: | Size: 93184 | Author: sam zeng | Hits:

[Communication-MobileE1_DCR

Description: 2MHz的数据时钟恢复电路,包括鉴相器、分频器及滤波器-2MHz data clock recovery circuit, including phase detector, divider and filter
Platform: | Size: 2048 | Author: Chen | Hits:

[Booksxapp868

Description: Clock data recovery .........good example
Platform: | Size: 393216 | Author: renu | Hits:

[VHDL-FPGA-Verilogshift

Description: E1接收部分主要功能是实现从输入的差分线路数据中恢复出2.048M线路时钟并将数据解码输出。包括解码和线路时钟恢复两模块。-E1 to receive some of the major functions of the difference from the input data lines to recover a clock and data lines 2.048M decoder output. Including decoding and clock recovery circuits of two modules.
Platform: | Size: 89088 | Author: liusen | Hits:

[VHDL-FPGA-Verilog5b6b

Description: 5B6B码是光纤数字通信系统中使用比较广泛的一种线路码型! 数据经过5B6B编码和并串转换后在光纤上传输,串行码序列中连续的比特0或比特1的长度不超过5,数据在0和1之间变换的密度很高,并具有直流平衡的特性,有利于接收电路和时钟恢复电路的设计。-5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or bit 1 of the length of not more than 5, data between 0 and 1, the high density of transformation, and has the characteristics of DC balance, favorable reception circuit and clock recovery circuit.
Platform: | Size: 3072 | Author: 王彬 | Hits:

[VHDL-FPGA-VerilogSERDES

Description: 基于Verilog的串并转换器的设计与实现,采用两种不同的方案来实现串并和并串转换的功能,并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE software simulation and debugging chipscope
Platform: | Size: 785408 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog5B6B

Description: FPGA的5B6B编译码器的设计代码可以编译而且有波形图 -5B6B code is used in fiber optic digital communication systems a more extensive line pattern! Data are 5B6B encoding and conversion, and string after the fiber transmission, serial code sequences in continuous bit 0 or bit 1 of the length of not more than 5, data between 0 and 1, the high density of transformation, and has the characteristics of DC balance, favorable reception circuit and clock recovery circuit.
Platform: | Size: 617472 | Author: 邓小虎 | Hits:

[VHDL-FPGA-Verilogxapp250

Description: xilinx 关于时钟数据恢复中的源代码-xilinx on the clock and data recovery in the source code
Platform: | Size: 12288 | Author: MML | Hits:

[matlabUp_timingBYM

Description: A timing error detector for Communication systems with simulink. # Required versions Matlab 5.2.1, Simulink 2.2.1 # File description 1. ti_det1.m (simulink version 5.2.1) An s-function to be used for timing detector. For detailed information, Refer to the following paper,K.H. Mueller and M. Mueller, Timing recovery in digital synchronous data receivers, IEEE Trans. Comun., vol COM-24, no. 5, May 1976. 2. m_delay3.m (related m-file) An s-function operating as sample and hold with clock port. 3. test1.mdl A timing recovery system to test the timing detector. -A timing error detector for Communication systems with simulink. # Required versions Matlab 5.2.1, Simulink 2.2.1 # File description 1. ti_det1.m (simulink version 5.2.1) An s-function to be used for timing detector. For detailed information, Refer to the following paper,K.H. Mueller and M. Mueller, Timing recovery in digital synchronous data receivers, IEEE Trans. Comun., vol COM-24, no. 5, May 1976. 2. m_delay3.m (related m-file) An s-function operating as sample and hold with clock port. 3. test1.mdl A timing recovery system to test the timing detector.
Platform: | Size: 156672 | Author: juyayayo | Hits:

[matlabqpsk_fast_symbol

Description: matlab代码实现一个快速时钟恢复的代码,这里可以看到一个具体的clock and data recovery的例子-it is about clock and data recovery,is a very useful tools to simulate the problems in communication!
Platform: | Size: 12288 | Author: naxieshijian | Hits:

[Program doc6.25g_dfe

Description: 高速数字传输技术, 时钟提取,均衡,高速采样 -high speed serdes, clock and data recovery, equalization, high-speed sampling
Platform: | Size: 443392 | Author: wai park | Hits:

[Program docsorna_agc_serdes

Description: 高速数字传输技术, 时钟提取,决策反馈均衡,高速采样, -high speed serdes, clock and data recovery, decision feedback-equalization, high-speed sampling
Platform: | Size: 339968 | Author: wai park | Hits:

[VHDL-FPGA-Verilogxapp224datarecovery

Description: Data recovery allows a receiver to extract embedded clock data from an incoming data stream. The receiver usually extracts the data from the incoming clock/data stream and then moves this data into a separate clock domain. Sometimes, the receiver’s clock is also used for onward data transmission. The circuit described in this application note provides a partial solution at data rates up to 160 Mb/s in a Virtex™ -E -7 device and a Spartan™ -IIE -6 device, up to 320 Mb/s for a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro -6 device. The solution is partial in the sense that no clock is actually recovered, but the data arriving is fully extracted. The speed is limited by the maximum frequency that can be accepted by the Data Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock, and another clock shifted by 90 degrees.
Platform: | Size: 68608 | Author: jia | Hits:

[androidaromafm-1.91-(1)

Description: Aroma is a file manager can work with Android devices on Recovery Mode like Clock World Mode CWM that can recover deleted data.
Platform: | Size: 1439744 | Author: Mohammad | Hits:

[Software Engineeringaaa

Description: 一种全数字时钟数据恢复电路的设计与实现,提出一种改进型超前滞后锁相环法的全数字时钟恢复算法,与同类电路比较,具有数据码率捕获范围宽、捕获时间短的优点。-Clock Date Recovery(CDR)circuit is a important part of data transmission equipment.For the burst data transmission,the traditional phase—lock loop can hardly achieve the requirement of fast synchronization. Whereof,this essay is trying to put forward an improved Lead and Lag Control a11-numeric CDR calculation,which is characterized with wide frequency capture range and rapid capture time.
Platform: | Size: 243712 | Author: 赵杰 | Hits:

[Industry researchSerDes

Description: 12.5 Gb/s半速率时钟数据恢复电路(CDR)的 设计及6.25Gb/s SerDes接收芯片的系统集成,设计工艺均为TSMC 0.189in CMOS工艺。-aspects:Design of Half-rate 1 2.5 Gb/s Clock Data Recovery (CDR)and Integration of 6.25Gb/s SerDes receiver.Both are realized in TSMC 0.1 89m CMOS process.
Platform: | Size: 12342272 | Author: 梧桐雨 | Hits:

[VHDL-FPGA-Verilogcdr

Description: 数据时钟恢复,采样8倍率高频时钟进行数据时钟恢复。已通过Modelsim仿真-Data and clock recovery, sampling 8 times the rate of high frequency clock for clock and data recovery. Have been through the Modelsim simulation
Platform: | Size: 1024 | Author: 王明明 | Hits:

[LabViewOpenClose_CDR

Description: 提供Agilent N4906设备的快速打开、关闭时钟数据恢复CDR的源码。-Agilent N4906 provides equipment to quickly open and close the clock data recovery CDR source.
Platform: | Size: 8192 | Author: 方芳 | Hits:

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