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[Other] dpsk

Description: 现代通信系统要求通信距离远、通信容量大、传输质量好。作为其关键技术之一的调制解调技术一直是人们研究的一 个重要方向。讨论和仿真实现了基于FPGA的数字化DPSK调制解调系统。用Altera公司的FPGA开发平台Quartus II 3.0实现了一 个对基带信号的DPSK调制解调系统模型的仿真。-Modern communication systems require communication distance, communication capacity, transmission quality. As part of its one of the key technologies of modem technology is that people have been an important direction of research. Discussion and simulation of FPGA-based digital DPSK modulation and demodulation system. FPGA using Altera
Platform: | Size: 446464 | Author: zhanghuan | Hits:

[VHDL-FPGA-Verilog] altera_solution

Description: altera的timing约束文档，很有帮助-altera of timing constraints files, helpful
Platform: | Size: 1386496 | Author: back1202 | Hits:

[Embeded-SCM Develop] USB_test

Description: Altera公司的NIOS2SOPC平台上的USB使用试验程序。 Quartus2软件版本5.0 NIOS2IDE软件版本5.0 硬件平台根据软件需求在Quartus2软件中构建。-Altera Corporation NIOS2SOPC platform USB using the test procedure. Quartus2 software version 5.0NIOS2IDE software version 5.0 hardware platform according to software requirements to build in Quartus2 software.
Platform: | Size: 22528 | Author: zt g | Hits:

[Post-TeleCom sofeware systems] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。-Altera
Platform: | Size: 1355776 | Author: YangJun | Hits:

[Special Effects] Video_and_mage_Processing

Description: The example design provides a framework for rapid development of video and image processing designs using the library of parameterizable MegaCore® functions available in the Altera Video and Image Processing Suite.
Platform: | Size: 1208320 | Author: 普林斯 | Hits:

[VHDL-FPGA-Verilog] Example-b4-1

Description: Altera基本宏功能应用设计实例  “\Example-b4-1\Project”目录下为设计工程  “\Example-b4-1\Solution”目录下为正确的解决方案，仅供读者参考 -Application of the basic macro features Altera Design
Platform: | Size: 303104 | Author: king | Hits:

[VHDL-FPGA-Verilog] Example-b4-2

Description: Altera IP应用设计实例  “\Example-b4-2\Project”目录下为设计工程  “\Example-b4-2\Solution”目录下为正确的解决方案，仅供读者参考 -Altera IP Application Design
Platform: | Size: 394240 | Author: king | Hits:

[VHDL-FPGA-Verilog] Example-b8-1

Description: 使用ModelSim对Altera设计进行功能仿真 对于没有使用到Altera的MegaWizard或LPM的设计而言，功能仿真比较简单，读者只需依据8.2.5小节描述的步骤依次执行即可，对于使用了MegaWizard或LPM的设计，则必需在仿真时指定相关的Altera库-Altera use ModelSim for functional simulation for designs that do not use Altera
Platform: | Size: 3923968 | Author: king | Hits:

[Software Engineering] Embedded_system_design_based_SOPC

Description: SOPC是Altera公司提出的一种灵活、高效的片上系统设计方案,它可以有选择地将处理器、存储器、I/O等系统设计需要的组件集成到一个PLD器件上。在SOPC设计中可方便地加入用户自定义逻辑。该文简要介绍了SOPC设计架构,然后通过一个实例,详细介绍了嵌入式系统中SOPC设计的实现方法和效果。-Altera Corporation SOPC is a flexible and efficient system-on-chip design, it can choose to have the processor, memory, I/O system design needs, such as components integrated into a PLD device. In SOPC design can be easily adding user-defined logic. The article briefly introduce the SOPC design framework, and then through an example of detailed SOPC embedded system design methods and results.
Platform: | Size: 173056 | Author: 郑宏超 | Hits:

[VHDL-FPGA-Verilog] 8255_OSED

Description: 8255A接口芯片的VHDL代码（ALTERA）
Platform: | Size: 226304 | Author: 尹福斌 | Hits:

[VHDL-FPGA-Verilog] jtag_logic

Description: 这是自制altera usb_blaster所用到的CPLD程序，用VHDL语言写的。
Platform: | Size: 2048 | Author: wdy2004 | Hits:

[VHDL-FPGA-Verilog] sditest

Description: 基于ep3c25的altera sdi ip核的使用，串并转换和并串转换-Ep3c25 based on the altera sdi ip nuclear use, and conversion and string and string conversion
Platform: | Size: 1477632 | Author: 林丹 | Hits:

[VHDL-FPGA-Verilog] DE2_USB_API

Description: Altera de2开发板提供的配套软件程序，用PC机上的应用软件来控制开发板外围器件，功能较全面-Altera de2 development board to provide the matching software program, used PC, application software to control the development board peripheral device, function more comprehensive
Platform: | Size: 9212928 | Author: 陈建 | Hits:

[SCM] DE2_UserManual

Description: Altera de2 开发板的使用指南，论述了DE2开发板所有配套实例的使用方法-Altera de2 development board
Platform: | Size: 2759680 | Author: 陈建 | Hits:

[Other] Cyclone_II

Description: Altera cycloneii 系列芯片资料，开发该系列FPGA器件需要了解其内部硬件资源-Altera cycloneii series chip data, the development of the series FPGA devices need to be aware of their internal hardware resources
Platform: | Size: 653312 | Author: 陈建 | Hits:

[VHDL-FPGA-Verilog] Nios

Description: Altera公司开发的用于其FPGA的的Nios软核入门介绍-Developed by Altera for its FPGA of the Nios soft-core entry-Introduction
Platform: | Size: 1537024 | Author: liukun | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram test controller altera -sdram test controller altera
Platform: | Size: 1519616 | Author: yangchun | Hits:

[VHDL-FPGA-Verilog] huawei_logic_Design

Description: FPGA逻辑设计，vhdl/verilog altera/xilinx 介绍-FPGA logic design, vhdl/verilog altera/xilinx Introduction
Platform: | Size: 2041856 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] flowled

Description: FPGA开发入门的Verilog HDL程序---流水灯,真实可用，验证通过，工程环境为Altera Quartus -FPGA development of Verilog HDL entry procedures- water lights, the real available, authentication is passed, the project environment for Altera Quartus
Platform: | Size: 193536 | Author: renyong0801 | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
Platform: | Size: 16384 | Author: zhyy | Hits:
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