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[VHDL-FPGA-Verilog] cpld-simple-program

Description: 在数字系统中常用的几个用AHDL语言编写的程序，用于大三学生的学习。-Commonly used in digital systems with several AHDL language program for junior students.
Platform: | Size: 5120 | Author: zhangmin | Hits:

[VHDL-FPGA-Verilog] ahdl--sine-wave-code-with-rom-look-up-table_imp.r

Description: hi this an verilog codes-hi this is an verilog codes
Platform: | Size: 8192 | Author: praha | Hits:

[VHDL-FPGA-Verilog] time

Description: 数字钟源代码程序，内有ahdl语言和原理图程序，已经仿真。-Digital clock source code, there ahdl language and schematic procedures have been simulation.
Platform: | Size: 188416 | Author: 小白 | Hits:

[VHDL-FPGA-Verilog] abel4

Description: ABEL开发工具，带反编译，将JED反编生成AHDL-failed to translate
Platform: | Size: 917504 | Author: lailinchun | Hits:

[VHDL-FPGA-Verilog] Baudrate_Generate

Description: AHDL语言编写，对输入的晶振频率经行分频处理，占空比可调的分频器-AHDL language, the crystal frequency on the input line sub-frequency, duty cycle adjustable divider
Platform: | Size: 312320 | Author: gzq | Hits:

[VHDL-FPGA-Verilog] SDRham-LA3BO

Description: AHDL Tutorial Power Point Presentation.
Platform: | Size: 1025024 | Author: mithun | Hits:

[Windows Develop] Tpinng_panngh

Description: 这是用AHDL语言开发的一个PCI采集系统的逻辑源码，其中的乒乓设计思思路新颖，有兴趣的朋友能参考一下！编译环境为maxplus2 可直接使用。 -AHDL language developed a PCI acquisition system logic source code, which the novel ping-pong the design Chaosisi Road, friends who are interested can refer to! Compilation environment for maxplus2 can be used directly.
Platform: | Size: 439296 | Author: 李 | Hits:

[Other] AHDL2006

Description: AHDL语言电子书 2006版 硬件控制语言-AHDL language book 2006 hardware control language
Platform: | Size: 268288 | Author: denglifu | Hits:

[Other] devider

Description: It s a EDA devider,write with AHDL language.
Platform: | Size: 3072 | Author: kay | Hits:

[Windows Develop] Tpinng_panngh

Description: 这是用AHDL语言开发的一个PCI采集系统的逻辑源码，其中的乒乓设计思思路新颖，有兴趣的朋友能参考一下！编译环境为maxplus2 可直接使用。-AHDL language developed a PCI acquisition system logic source code, which the novel ping-pong the design Chaosisi Road, friends who are interested can refer to! Compilation environment for maxplus2 can be used directly.
Platform: | Size: 439296 | Author: oodpr | Hits:

[Internet-Network] timer

Description: AHDL parametrized timer - for Altera Quartus compiler only-AHDL parametrized timer- for Altera Quartus compiler only
Platform: | Size: 1024 | Author: eseco | Hits:

[Software Engineering] Quartusii11_13192

Description: 用于quartus，适用于vhdl、ahdl的设计，适用win7等系统-Designed for quartus, applicable to vhdl, ahdl applicable win7 systems
Platform: | Size: 13312 | Author: zhng | Hits:

[SCM] jiaotongdeng

Description: 十字路口交通管理信号灯设计与制作，是电子学课程设计，用了硬件搭建以及AHDL语言-Intersection traffic signal design and production management, e-learning courses are designed and built with the hardware AHDL language
Platform: | Size: 3072 | Author: lifen | Hits:

[Other Embeded program] snake

Description: 单片机上开发的贪食蛇小游戏，ahdl实现，新手开发。-little game developed for SCM, ahdl
Platform: | Size: 604160 | Author: Rain | Hits:

[Other] Quartus

Description: Quartus II完全教程 内部资料 提供了完全集成且与电路结构无关的开发包环境，具有数字逻辑设计的全部特性，包括： 可利用原理图、结构框图、VerilogHDL、AHDL和VHDL完成电路描述，并将其保存为设计实体文件；芯片（电路）平面布局连线编辑等-Quartus II complete tutorial provides a fully integrated internal data and independent of the circuit structure of the development package environment, with all the characteristics of digital logic design, including: Available schematics, block diagram, VerilogHDL, AHDL and VHDL complete circuit description, and save it as a design entity files chip (circuit) connection layout editing
Platform: | Size: 7505920 | Author: 刘欣 | Hits:

[Other] VHDLCode_8bitCPU

Description: 这是计算机组成原理的课程设计，将16位CPU改造成8位流水线CPU，AHDL语言，这是改造完成的源代码。-This is a computer composition principle of curriculum design, the 16-bit CPU transformed into eight pipeline CPU, AHDL language, which is the transformation was complete source code.
Platform: | Size: 920576 | Author: 薛成 | Hits:

[VHDL-FPGA-Verilog] 10419729vhdl对数

Description: 进行对数运算的IP核，可以计算以2，10，e为底的对数，最高可输入24bit宽度的数据。 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。(The IP kernel that performs logarithmic operations can compute data at the base of 2, 10, and E, with the highest input 24bit width. Written in AHDL language, can be used in MaxplusII and QuartusII, source code encryption.)
Platform: | Size: 116736 | Author: wove2006 | Hits:

[VHDL-FPGA-Verilog] ZXM-SoundCard Extreme rev01 Source

Description: ZXM-SoundCard Extreme rev01 Source (AHDL)
Platform: | Size: 146859 | Author: lvdpidor | Hits:
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